yosys.git
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Miodrag MilanovićMerge pull request #1413 from YosysHQ/mmicko/backend_bi...
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-29 Henner ZellerAvoid work in replace() if rules empty.
2019-09-28 Miodrag MilanovicAdd aiger and protobuf backends binary support
2019-09-28 Miodrag MilanovicSupport binary files for backends, fixes #1407
2019-09-28 Eddie HungFix box name
2019-09-27 Eddie HungRe-order
2019-09-27 Eddie HungMissing (* mul2dsp *) for sliceB
2019-09-27 Eddie HungOoops AREG and BREG to default to -1
2019-09-27 Aman GoelCorrects btor2 backend
2019-09-27 Marcin KościelnickiFix _TECHMAP_REMOVEINIT_ handling.
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-27 Miodrag MilanovićMerge pull request #1409 from YosysHQ/mmicko/fix_getopt...
2019-09-27 Miodrag MilanovicChange order of parameters, to work on other os
2019-09-27 Clifford WolfMerge pull request #1404 from YosysHQ/fix_gzip_macos
2019-09-26 Eddie HungUpdate doc with max cascade chain of 20
2019-09-26 Eddie HungDo not always zero out C (e.g. during cascade breaks)
2019-09-26 Eddie HungUpdate doc
2019-09-26 Eddie HungZero out ports
2019-09-26 Eddie Hungxilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 Eddie HungTry recursive pmgen for P cascade
2019-09-26 Eddie HungMissing an '&'
2019-09-26 Eddie HungCombine 'flatten' & 'coarse' labels in synth_ecp5 so...
2019-09-26 Miodrag MilanovicMake read/write gzip files on macos works, fixes #1357
2019-09-26 Eddie HungTypo
2019-09-26 Eddie HungCREG to check for \keep
2019-09-26 Eddie HungRemove newline
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-26 Eddie Hungmul2dsp.v slice names
2019-09-26 Eddie HungDo not die if DSP48E1.P has no users (would otherwise...
2019-09-26 Eddie HungReject if (* init *) present
2019-09-26 Eddie HungRemove unnecessary check for A_SIGNED != B_SIGNED;...
2019-09-26 Eddie HungRevert "Remove _TECHMAP_CELLTYPE_ check since all ...
2019-09-26 Eddie HungRevert "No need for $__mul anymore?"
2019-09-26 Eddie HungRework xilinx_dsp postAdd for new wreduce call
2019-09-26 Eddie HungOnly wreduce on t:$add
2019-09-25 Eddie HungRemove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 Eddie HungFix memory issue since SigSpec& could be invalidated
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
2019-09-25 Eddie HungNo need for $__mul anymore?
2019-09-25 Eddie Hungunextend only used in init
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Eddie HungOops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-25 SergeyDegtyarChange sync controls to async.
2019-09-25 Clifford WolfMerge pull request #1402 from YosysHQ/clifford/portlist
2019-09-25 Clifford WolfImprove "portlist" command
2019-09-24 Clifford WolfAdd "portlist" command
2019-09-24 SergeyDegtyaradffs test update (equiv_opt -multiclock).
2019-09-24 Eddie HungAdd (* techmap_autopurge *) to abc_unmap.v too
2019-09-24 Eddie Hung"abc_padding" attr for blackbox outputs that were padde...
2019-09-24 Eddie HungForce $inout.out ports to begin with '$' to indicate...
2019-09-24 Eddie HungAdd techmap_autopurge to outputs in abc_map.v too
2019-09-24 Eddie HungRevert "Add a xilinx_finalise pass"
2019-09-24 Eddie HungRevert "Remove (* techmap_autopurge *) from abc_unmap...
2019-09-24 Eddie HungRevert "Vivado does not like zero width port connections"
2019-09-24 Eddie HungVivado does not like zero width port connections
2019-09-24 Eddie HungRemove (* techmap_autopurge *) from abc_unmap.v since...
2019-09-24 Eddie HungAdd a xilinx_finalise pass
2019-09-23 Eddie HungSet [AB]CASCREG to legal values
2019-09-23 Eddie HungComment to explain separating CREG packing
2019-09-23 Eddie HungSeparate out CREG packing into new pattern, to avoid...
2019-09-23 Eddie HungMove log_debug("\n") later
2019-09-23 Eddie HungMove unextend initialisation later
2019-09-23 Eddie HungUse new port() overload once more
2019-09-23 Miodrag MilanovićMerge pull request #1399 from nakengelhardt/fix-show...
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 N. Engelhardtadd xdot dependency to Brewfile
2019-09-23 N. Engelhardtfix show command for macos
2019-09-21 Clifford WolfMerge pull request #1392 from YosysHQ/eddie/fix1391
2019-09-21 Eddie HungHell let's add the original #1381 testcase too
2019-09-21 Eddie HungRevert abc9.cc
2019-09-21 Eddie HungAdd testcase
2019-09-21 Eddie HungTrim mismatched connection to be same (smallest) size
2019-09-21 Eddie HungFix first testcase in #1391
2019-09-20 Eddie HungGrammar
2019-09-20 Eddie HungUse new port/param overload in pmg
2019-09-20 Eddie HungOutput pattern matcher items as log_debug()
2019-09-20 Eddie HungOPMODE is port not param
2019-09-20 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungDo not run xilinx_dsp_cascadeAB for now
2019-09-20 Eddie HungWIP for xiinx_dsp_cascadeAB
2019-09-20 Eddie HungRun until convergence
2019-09-20 Eddie HungCleanup ice40_dsp.pmg
2019-09-20 Eddie HungCleanup xilinx_dsp
2019-09-20 Eddie HungMore exceptions
2019-09-20 Eddie HungFix signedness bug
2019-09-20 Eddie HungUpdate doc
2019-09-20 Eddie HungAdd a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 Eddie HungAdd an overload for port/param with default value
2019-09-20 Eddie HungRe-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
2019-09-20 Eddie HungRevert "Move mul2dsp before wreduce"
2019-09-20 Eddie HungMove mul2dsp before wreduce
2019-09-20 Eddie HungSmall cleanup
2019-09-20 Clifford WolfMerge pull request #1386 from YosysHQ/clifford/fix1360
2019-09-20 Clifford WolfFix handling of read_verilog config in AstModule::repro...
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