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litex.git
2012-01-28
Sebastien Bourdeauducq
fhdl: do not prefix instance signal names
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2012-01-27
Sebastien Bourdeauducq
Remove explicit bus names and rely on the new automatic...
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2012-01-27
Sebastien Bourdeauducq
fhdl: support memory read enable
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2012-01-27
Sebastien Bourdeauducq
fhdl: make WRITE_FIRST default
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2012-01-27
Sebastien Bourdeauducq
doc: memories
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2012-01-27
Sebastien Bourdeauducq
fhdl: memories working
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2012-01-27
Sebastien Bourdeauducq
fhdl/verilog: clean up signal classification and suppor...
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2012-01-27
Sebastien Bourdeauducq
fhdl/structure: memory description
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2012-01-27
Sebastien Bourdeauducq
doc: cosmetic changes
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2012-01-26
Sebastien Bourdeauducq
doc: ASMI description
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2012-01-25
Sebastien Bourdeauducq
Remove duplicate logo
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2012-01-25
Sebastien Bourdeauducq
doc: refactor
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2012-01-21
Sebastien Bourdeauducq
flow/ala: fix typo for And (thanks Lars)
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2012-01-21
Sebastien Bourdeauducq
Logo
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2012-01-20
Sebastien Bourdeauducq
Use meaningful class names
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2012-01-20
Sebastien Bourdeauducq
Include fragment pads in pre-naming dictionary
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2012-01-20
Sebastien Bourdeauducq
namer/trace_back: behave on None code_context
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2012-01-20
Sebastien Bourdeauducq
Fix instance support
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2012-01-20
Sebastien Bourdeauducq
Include unused I/Os in pre-naming dictionary and regist...
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2012-01-20
Sebastien Bourdeauducq
Remove NoContext
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2012-01-19
Sebastien Bourdeauducq
Only include context prefix when necessary
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2012-01-19
Sebastien Bourdeauducq
Fix disjoint namespace test
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2012-01-19
Sebastien Bourdeauducq
Always include last step in names
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2012-01-19
Sebastien Bourdeauducq
New naming system: second attempt
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2012-01-16
Sebastien Bourdeauducq
examples/corelogic_conv: use two dividers
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2012-01-16
Sebastien Bourdeauducq
corelogic/record: empty default name
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2012-01-16
Sebastien Bourdeauducq
New naming system beginning to work
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2012-01-16
Sebastien Bourdeauducq
fhdl: new naming system (broken)
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2012-01-15
Sebastien Bourdeauducq
actorlib/control: 'for' generator
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2012-01-15
Sebastien Bourdeauducq
dma_wishbone: small syntax simplification thanks to...
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2012-01-15
Sebastien Bourdeauducq
fhdl: allow None statements
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2012-01-15
Sebastien Bourdeauducq
wishbone_dma: convert to new endpoint API and fix some...
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2012-01-15
Sebastien Bourdeauducq
bus: list signals
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2012-01-15
Sebastien Bourdeauducq
flow: saner endpoint management
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2012-01-13
Sebastien Bourdeauducq
Wishbone: omit fixed LSBs
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2012-01-10
Sebastien Bourdeauducq
actorlib: Wishbone DMA read master (WIP)
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2012-01-10
Sebastien Bourdeauducq
record: return offset
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2012-01-10
Sebastien Bourdeauducq
flow: simplify actor fragment interface
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2012-01-09
Sebastien Bourdeauducq
record: support aligned flattening
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2012-01-09
Sebastien Bourdeauducq
corelogic: FSM
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2012-01-09
Sebastien Bourdeauducq
record: cleanup
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2012-01-09
Sebastien Bourdeauducq
record: better exception code
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2012-01-09
Sebastien Bourdeauducq
record: preserve order
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2012-01-09
Sebastien Bourdeauducq
flow: draw network graph
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2012-01-09
Sebastien Bourdeauducq
flow: actor busy signal
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2012-01-08
Sebastien Bourdeauducq
Composer (WIP)
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2012-01-07
Sebastien Bourdeauducq
endpoint: add _i/_o suffix on signal names
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2012-01-07
Sebastien Bourdeauducq
fhdl: better signal naming heuristic
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2012-01-07
Sebastien Bourdeauducq
constant: equality
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2012-01-07
Sebastien Bourdeauducq
verilog: split comb block, use assign statements
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2012-01-06
Sebastien Bourdeauducq
convtools -> tools
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2012-01-06
Sebastien Bourdeauducq
flow: network
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2012-01-06
Sebastien Bourdeauducq
record: compatibility check
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2012-01-06
Sebastien Bourdeauducq
flow: plumbing
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2012-01-06
Sebastien Bourdeauducq
actor: simplified automatic control
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2012-01-06
Sebastien Bourdeauducq
ALA: use records for tokens
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2012-01-06
Sebastien Bourdeauducq
README: update copyright year
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2012-01-06
Sebastien Bourdeauducq
corelogic: record
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2012-01-06
Sebastien Bourdeauducq
Signal repr
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2012-01-05
Sebastien Bourdeauducq
Merge branch 'master' of github.com:milkymist/migen
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2012-01-05
Sebastien Bourdeauducq
Convert -> convert
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2011-12-27
Alain Péteut
setup.py: fix to catch all modules
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2011-12-24
Alain Péteut
Add setup script
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2011-12-22
Sebastien Bourdeauducq
example: flow conversion
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2011-12-22
Sebastien Bourdeauducq
flow: sum and division actors
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2011-12-22
Sebastien Bourdeauducq
fhdl: encapsulate replicated constants
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2011-12-22
Sebastien Bourdeauducq
flow: actor class
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2011-12-22
Sebastien Bourdeauducq
csr: use optree
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2011-12-22
Sebastien Bourdeauducq
corelogic: operator tree
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2011-12-21
Sebastien Bourdeauducq
verilog: comb reset
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2011-12-21
Sebastien Bourdeauducq
verilog: break down Convert function
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2011-12-21
Sebastien Bourdeauducq
verilog: ignore variable property in combinatorial...
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2011-12-21
Sebastien Bourdeauducq
Consistent names
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2011-12-19
Sebastien Bourdeauducq
README: Flow
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2011-12-19
Sebastien Bourdeauducq
README: Core Logic, Bus, Bank
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2011-12-19
Sebastien Bourdeauducq
README: structure + FHDL description
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2011-12-18
Sebastien Bourdeauducq
examples: remove old-style declarations
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2011-12-18
Sebastien Bourdeauducq
corelogic: fix signal exports
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2011-12-18
Sebastien Bourdeauducq
fhdl: better matching of assignment
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2011-12-18
Sebastien Bourdeauducq
Remove uses of declare_signal
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2011-12-18
Sebastien Bourdeauducq
fhdl: also take into account object attributes in _make...
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2011-12-18
Sebastien Bourdeauducq
fhdl: automatic signal name from assignment
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2011-12-17
Sebastien Bourdeauducq
bank: support raw registers
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2011-12-17
Sebastien Bourdeauducq
fhdl: fix series of if/elif/else
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2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
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2011-12-17
Sebastien Bourdeauducq
verilog: get the simulator to run the combinatorial...
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2011-12-17
Sebastien Bourdeauducq
verilog: support for float parameters in instances
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2011-12-16
Sebastien Bourdeauducq
verilog: user-definable reset and clock
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2011-12-16
Sebastien Bourdeauducq
fhdl: simpler syntax
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2011-12-16
Sebastien Bourdeauducq
Pay a bit more attention to PEP8
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2011-12-13
Sebastien Bourdeauducq
wishbone2csr: wait for WB deack
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2011-12-13
Sebastien Bourdeauducq
timeline: only trigger in rest state
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2011-12-13
Sebastien Bourdeauducq
examples: Wishbone interconnect test bench
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2011-12-13
Sebastien Bourdeauducq
verilog: use blocking assignment in combinatorial process
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2011-12-13
Sebastien Bourdeauducq
wishbone: decoder: fix slave cyc generation in register...
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2011-12-12
Sebastien Bourdeauducq
wishbone2csr: fix double-write bug
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2011-12-12
Sebastien Bourdeauducq
wishbone: only send ack to the active master in arbiter
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2011-12-12
Sebastien Bourdeauducq
fhdl: allow a namespace to be specified for Verilog...
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2011-12-11
Sebastien Bourdeauducq
fhdl: support Constant parameters for Verilog conversion
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2011-12-11
Sebastien Bourdeauducq
fhdl: fix list references (thanks Lars)
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