yosys.git
2013-09-17 Clifford WolfImprovements in EDIF backend
2013-09-15 Clifford WolfAdded additional options to BLIF backend
2013-09-15 Clifford WolfAdded BLIF backend
2013-09-15 Clifford WolfA couple of small fixes in SPICE backend
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-09-15 Clifford WolfUpdated manual
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-09-03 Clifford WolfAdded -selected option to various backends
2013-08-28 Clifford WolfEncode large (>32 bits) parameters as hex string in...
2013-08-27 Clifford WolfImproved edif backend
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes...
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files
2013-08-22 Clifford WolfMore explicit integer output in verilog backend
2013-08-22 Clifford WolfAdded correct encoding of identifiers in EDIF backend
2013-08-22 Clifford WolfAdded edif backend (still under construction)
2013-08-21 Clifford WolfMerge pull request #10 from hansiglaser/master
2013-08-21 Clifford WolfSome minor documentation fixes
2013-08-21 Johann Glaserfixed Verilog parser filename and line numbering issue...
2013-08-20 Clifford WolfMerge pull request #9 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for include directories with the new...
2013-08-20 Clifford WolfMerge pull request #8 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for notif0/notif1 primitives
2013-08-20 Clifford WolfAdded cleaning of old version_* files to version_*...
2013-08-20 Clifford WolfAdded version info to yosys command and added -V option
2013-08-20 Clifford WolfMinor fixes in abc build instructions and abc pass
2013-08-19 Clifford WolfFixed width and sign detection for ** operator
2013-08-19 Clifford WolfAdded support for bufif0/bufif1 primitives
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend)
2013-08-15 Clifford WolfImplemented same div-by-zero behavior as found in other...
2013-08-15 Clifford WolfFixed signed div/mod in const eval (rounding and stuff)
2013-08-15 Clifford WolfAdded ezsat api for creation of anonymous vectors
2013-08-15 Clifford WolfAdded sat -ignore_div_by_zero switch
2013-08-15 Clifford WolfAdded eval -brute_force_equiv_checker_x mode
2013-08-12 Clifford WolfAdded support for "2**n" shifter encoding
2013-08-11 Clifford WolfAdded SAT support for $div and $mod cells
2013-08-11 Clifford WolfAdded "clean -purge" and ";;;" support
2013-08-11 Clifford WolfAdded ";;" as shortcut for "; clean;"
2013-08-10 Clifford Wolffreduce performance fix
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-08-09 Clifford WolfAdded techmap -opt mode
2013-08-09 Clifford WolfSome fixes to improve determinism
2013-08-08 Clifford WolfSort ctrl signals in fsm_extract
2013-08-08 Clifford WolfAdded -try option to freduce pass
2013-08-08 Clifford WolfAdded "clean" command (less verbose opt_clean)
2013-08-07 Clifford WolfFixed topological ordering in freduce pass
2013-08-07 Clifford WolfImproved handling of private names in opt_clean and...
2013-08-07 Clifford WolfAdded stubnets example to manual prog chapter
2013-08-06 Clifford WolfSmall bugfixes in freduce pass
2013-08-06 Clifford WolfAdded freduce command
2013-08-06 Clifford WolfFixed SigPool::del() method
2013-08-06 Clifford WolfAdded proper deallocation of history buffer
2013-08-01 Clifford WolfUpdated TODO section in README
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load)
2013-07-25 Clifford WolfAdded "help -write-web-command-reference-manual"
2013-07-25 Clifford WolfFixed comments in manual rtlil/ilang syntax
2013-07-25 Clifford WolfAdded RTLIL and Liberty syntax highlighting to manual
2013-07-24 Clifford WolfAutomatically run "proc" on extract map files
2013-07-23 Clifford WolfAdded $lut cells and abc lut mapping support
2013-07-23 Clifford WolfFixed "make clean" for manual files
2013-07-21 Clifford WolfAdded web site link to README
2013-07-20 Clifford WolfAdded Yosys Manual
2013-07-12 Clifford WolfMore fixes in ternary op sign handling
2013-07-11 Clifford WolfFixed sign handling in ternary operator
2013-07-11 Clifford WolfAdded ast frontend refactoring to TODO
2013-07-11 Clifford WolfAnother vloghammer related bugfix
2013-07-10 Clifford WolfBugfixes for empty signal vectors
2013-07-09 Clifford WolfFixed sign propagation in bit-wise operators
2013-07-09 Clifford WolfMore fixes in ast expression sign/width handling
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-07-09 Clifford WolfFixed shift ops with large right hand side
2013-07-09 Clifford WolfMajor redesign of expr width/sign detecion (verilog...
2013-07-07 Clifford WolfFixed another bug found using vloghammer
2013-07-07 Clifford WolfFixed AST_CONSTANT node generation
2013-07-07 Clifford WolfRemoved tests/xsthammer
2013-07-07 Clifford WolfAdded opt_clean -purge option
2013-07-07 Clifford WolfFixed handling of $eq and $ne in opt_const
2013-07-05 Clifford WolfFixed vivado related xsthammer bugs
2013-07-05 Clifford WolfVarious improvements in xsthammer report generator
2013-07-05 Clifford WolfAdded work-around to isim bug in xsthammer report script
2013-07-05 Clifford WolfFixed gcc warnings in ezminisat
2013-07-05 Clifford WolfAdded CARRY4 Xilinx cell to xsthammer cell lib
2013-07-05 Clifford WolfAdded xsthammer report generator
2013-07-04 Clifford WolfImproved xsthammer quartus support
2013-07-04 Clifford WolfAdded Altera Cyclon III cell library to xsthammer
2013-07-04 Clifford WolfDocumentation updates
2013-07-04 Clifford WolfAdded defparam support to Verilog/AST frontend
2013-07-03 Clifford WolfAdded QMAKE makefile variable
2013-07-03 Clifford WolfAdded Altera Quartus support to xsthammer
2013-07-03 Clifford WolfProgress in xsthammer
2013-06-26 Clifford WolfAdded vivado support to xsthammer
2013-06-23 Clifford WolfAdded SAT support for -all/-max with -verify
2013-06-20 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-06-20 Clifford WolfAdded timout functionality to SAT solver
2013-06-19 Clifford WolfAdded renaming of wires and cells to "rename" command
2013-06-19 Clifford WolfAdded "eval" pass
2013-06-18 Clifford WolfFixed build with clang
2013-06-18 Clifford WolfAdded splitnets command
2013-06-18 Clifford WolfAdded RTLIL::Module::fixup_ports() API and RTLIL::...
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