yosys.git
2019-12-18 Eddie HungBump ABC for upstream fix
2019-12-18 Eddie HungUse pool<> instead of std::set<> to preserver ordering
2019-12-17 Eddie Hungaiger frontend to user shorter, $-prefixed, names
2019-12-17 Eddie HungCleanup xaiger, remove unnecessary complexity with...
2019-12-17 Eddie Hungread_xaiger to cope with optional '\n' after 'c'
2019-12-17 Eddie HungDo not sigmap
2019-12-17 Eddie HungRevert "Use sigmap signal"
2019-12-17 Eddie Hungabc9 needs a clean afterwards
2019-12-17 Eddie HungPut $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-17 Eddie HungUse sigmap signal
2019-12-16 Eddie HungSkip $inout transformation if not a PI
2019-12-16 Eddie HungRevert "write_xaiger: use sigmap bits more consistently"
2019-12-16 Eddie Hungwrite_xaiger: use sigmap bits more consistently
2019-12-14 Eddie HungName inputs/outputs of aiger 'i%d' and 'o%d'
2019-12-12 Eddie HungRemove 'clkpart' entry in CHANGELOG
2019-12-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Eddie HungUpdate README.md :: abc_ -> abc9_
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
2019-12-09 Eddie HungFix comment
2019-12-09 Eddie Hungice40_opt to restore attributes/name when unwrapping
2019-12-09 Eddie Hungice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 Eddie Hungunmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 Eddie Hung-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 Eddie HungSensitive to direct inst of $__ICE40_CARRY_WRAPPER...
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ...
2019-12-07 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx...
2019-12-07 Eddie HungDrop keep=0 attributes on SB_CARRY
2019-12-07 Eddie HungCall abc9 with "&write -n", and parse_xaiger() to cope
2019-12-07 Eddie HungRemove creation of $abc9_control_wire
2019-12-07 Eddie HungDo not connect undriven POs to 1'bx
2019-12-07 Eddie HungFix abc9 re-integration, remove abc9_control_wire,...
2019-12-07 Eddie HungFix writing non-whole modules, including inouts and...
2019-12-06 Jan Kowalewskitests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 Eddie Hungabc9 to use mergeability class to differentiate sync...
2019-12-06 Eddie Hungwrite_xaiger to support part-selected modules again
2019-12-06 Eddie Hungabc9 to do clock partitioning again
2019-12-06 Eddie HungRemove clkpart
2019-12-05 Eddie HungRevert "Special abc9_clock wire to contain only clock...
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungMerge SB_CARRY+SB_LUT4's attributes when creating ...
2019-12-05 Eddie HungAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 Eddie HungMissing wire declaration
2019-12-05 Eddie Hungabc9_map.v to transform INIT=1 to INIT=0
2019-12-05 Eddie HungOh deary me
2019-12-05 Eddie HungBump ABC to get "&verify -s" fix
2019-12-05 Eddie Hungoutput reg Q -> output Q to suppress warning
2019-12-05 Eddie Hungabc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 whitequarkkernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ...
2019-12-04 whitequarkmanual: document behavior of many comb cells more preci...
2019-12-04 Marcin Kościelnickixilinx: Add tristate buffer mapping. (#1528)
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping...
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537)
2019-12-04 Eddie HungCleanup
2019-12-04 Eddie HungAdd assertion
2019-12-04 Eddie Hungwrite_xaiger to consume abc9_init attribute for abc9_flops
2019-12-04 Eddie HungAdd abc9_init wire, attach to abc9_flop cell
2019-12-03 Eddie HungRevert "Add INIT value to abc9_control"
2019-12-03 Eddie HungUpdate ABCREV for upstream bugfix
2019-12-03 Eddie HungCheck SB_CARRY name also preserved
2019-12-03 Eddie Hung$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for...
2019-12-03 Eddie Hungice40_opt to ignore (* keep *) -ed cells
2019-12-03 Eddie Hungice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 Eddie HungAdd testcase
2019-12-03 Eddie Hungtechmap abc_unmap.v before xilinx_srl -fixed
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de Vosupdate test
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 Eddie HungAdd INIT value to abc9_control
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
2019-12-02 Eddie HungCleanup
2019-12-02 Eddie HungUse pool instead of std::set for determinism
2019-12-02 Eddie HungUse pool<> not std::set<> for determinism
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds...
2019-12-01 David Shahabc9: Fix breaking of SCCs
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL.
2019-11-28 Eddie Hungclkpart -unpart into 'finalize'
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-28 Eddie HungMove \init signal for non-port signals as long as inter...
2019-11-28 Eddie HungRevert "Fold loop"
2019-11-27 Marcin Kościelnickiread_ilang: do bounds checking on bit indices
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd multiple driver testcase
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd comment, use sigmap
2019-11-27 Eddie HungRevert "Fold loop"
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie Hungean call after abc{,9}
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungDo not replace constants with same wire
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
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