yosys.git
2020-04-27 Vamsi K VytlaPreserve 'signed'-ness of a verilog wire through RTLIL
2020-04-24 Claire WolfMerge pull request #1995 from YosysHQ/eddie/fix_verific...
2020-04-24 Dan Ravensloftintel_alm: cleanup duplication
2020-04-23 Eddie Hungverific: do not assert if wire not found; warn instead
2020-04-23 Eddie HungMerge pull request #1974 from YosysHQ/eddie/abc9_disabl...
2020-04-23 Claire WolfMerge pull request #1989 from boqwxp/qbfsat_anyconst_so...
2020-04-23 Claire WolfMerge pull request #1988 from boqwxp/qbfsat
2020-04-23 Claire WolfMerge pull request #1986 from YosysHQ/eddie/verific_enum
2020-04-23 Dan Ravensloftintel_alm: work around a Quartus ICE
2020-04-23 Alberto Gonzalezqbfsat: Make hole name recovery more robust. Allow...
2020-04-23 Eddie HungMerge pull request #1984 from YosysHQ/eddie/getParam_ex...
2020-04-23 Alberto Gonzalezqbfsat: Add `-assume-negative-polarity` option.
2020-04-23 Eddie Hungecp5: ecp5_gsr to skip cells that don't have GSR parame...
2020-04-23 Eddie Hungtests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-23 Eddie Hungxilinx: xilinx_dsp_cascade to check CREG for DSP48E1...
2020-04-23 Eddie Hungverific: import enum attributes from verific
2020-04-22 Eddie Hungtest: ice40_dsp test to read +/ice40/cells_sim.v for...
2020-04-22 Eddie Hungxilinx: improve xilinx_dffopt message
2020-04-22 Eddie Hungxilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 Eddie Hungkernel: Cell::getParam() to throw exception again if...
2020-04-22 Eddie HungMerge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 Eddie HungMerge pull request #1983 from YosysHQ/eddie/use_default...
2020-04-22 whitequarkMerge pull request #1982 from AsuMagic/asu/cxxrtl-memor...
2020-04-22 Claire WolfUpdate passes/cmds/select.cc
2020-04-22 Eddie HungMerge pull request #1969 from boqwxp/pool_emplace
2020-04-22 Eddie HungCleanup use of hard-coded default parameters in light...
2020-04-22 Asucxxrtl: keep the memory write queue sorted on insertion.
2020-04-22 Eddie HungMerge pull request #1973 from YosysHQ/eddie/fix1966
2020-04-22 Eddie Hungtests: update select black/white-box tests
2020-04-22 Eddie Hungselect: do not select black/white boxes by default...
2020-04-22 Eddie HungMerge pull request #1950 from YosysHQ/eddie/design_import
2020-04-22 Eddie Hungyosys-config: spelling
2020-04-22 Eddie Hungtests: use `yosys-config --datdir` instead of hard...
2020-04-22 Eddie Hungpool: add emplace() function
2020-04-22 Claire WolfMerge pull request #1976 from YosysHQ/dave/fix-sim...
2020-04-22 Claire WolfMerge pull request #1979 from whitequark/cxxrtl-go...
2020-04-22 whitequarkcxxrtl: run edge detectors only once in eval().
2020-04-22 whitequarkcxxrtl: add an unsupported knob for manipulating clock...
2020-04-21 whitequarkcxxrtl: use log_id() where appropriate. NFC.
2020-04-21 Marcelina Kościelnickabugpoint: Don't remove modules or cells while iterating...
2020-04-21 whitequarkcxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black...
2020-04-21 whitequarkcxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
2020-04-21 Dan Ravensloftintel_alm: Documentation improvements
2020-04-21 Alberto Gonzalezkernel: Rename arguments to rvalue-reference-accepting...
2020-04-21 Marcelina Kościelnickawrite_json: dump default parameter values
2020-04-21 Marcelina KościelnickaUse default parameter value in getParam
2020-04-21 Marcelina Kościelnickahierarchy: Convert positional parameters to named.
2020-04-21 Marcelina Kościelnickailang, ast: Store parameter order and default value...
2020-04-21 Marcelina Kościelnickaidict: Make iterator go forward.
2020-04-21 Claire WolfMerge pull request #1971 from YosysHQ/claire/edifkeep
2020-04-21 Claire WolfMerge pull request #1851 from YosysHQ/claire/bitselwrite
2020-04-21 whitequarkcxxrtl: use one delta cycle for immediately converging...
2020-04-21 whitequarkcxxrtl: add -O6, a shortcut for running `proc; flatten`.
2020-04-21 whitequarkcxxrtl: unbuffer module input wires.
2020-04-21 whitequarkcxxrtl: simplify generated edge detection logic.
2020-04-21 whitequarkcxxrtl: localize wires with multiple comb drivers,...
2020-04-21 whitequarkcxxrtl: detect buffered comb wires, not just feedback...
2020-04-21 Claire WolfAdd '=' selection pattern prefix for non-blackbox only...
2020-04-21 Claire WolfImprove net priorities in EDIF back-end
2020-04-21 David Shahsim: Fix handling of constant-connected cell inputs...
2020-04-21 whitequarkMerge pull request #1961 from whitequark/paramod-origin...
2020-04-20 Eddie Hungtests: remove write_ilang
2020-04-20 Eddie HungMerge pull request #1975 from dh73/claire/bitselwrite
2020-04-20 Eddie HungRemove '-ignore_unknown_cells' option from 'sat'
2020-04-20 Eddie HungSimplify test case script
2020-04-20 Eddie HungRemove ununsed files
2020-04-20 Eddie HungMerge pull request #1972 from YosysHQ/eddie/bug1970
2020-04-20 Eddie Hungabc9: tolerate ABC nonzero exit code if output.aig...
2020-04-20 diegoModifications of tests as per Eddie's request
2020-04-20 Eddie Hungxilinx/ecp5: disable abc9's "&mfs" optimisation
2020-04-20 Eddie Hungabc9: -prep_lut to be more robust
2020-04-20 Eddie Hungabc9: add testcase reduced from #1970
2020-04-20 Claire WolfIgnore conflicting keep attributes, unless asked not...
2020-04-20 Claire WolfMerge pull request #1964 from YosysHQ/claire/sformatf
2020-04-20 Alberto GonzalezAdd rvalue-reference-accepting `entry_t` constructor...
2020-04-20 Alberto GonzalezIn `pool`, construct `entry_t`s in-place and add an...
2020-04-19 whitequarkMerge pull request #1967 from whitequark/cxxrtl-blackbo...
2020-04-19 whitequarkcxxrtl: provide attributes to black box factories,...
2020-04-18 Claire WolfExtend support for format strings in Verilog front-end
2020-04-18 whitequarkMerge pull request #1963 from whitequark/cxxrtl-blackboxes
2020-04-18 whitequarkcxxrtl: add templated black box support.
2020-04-18 whitequarkcxxrtl: make eval() and commit() inline in blackboxes.
2020-04-18 whitequarkcxxrtl: add simple black box support.
2020-04-18 whitequarkcxxrtl: use ID::X instead of ID(X). NFC.
2020-04-18 whitequarkast, rpc: record original name of $paramod\* as \hdlnam...
2020-04-17 whitequarkMerge pull request #1955 from whitequark/cxxrtl-sync_always
2020-04-17 whitequarkMerge pull request #1952 from boqwxp/add_edge_location
2020-04-17 diegoWrong fixed value
2020-04-17 whitequarkcxxrtl: correctly handle `sync always` rules.
2020-04-17 whitequarkMerge pull request #1954 from YosysHQ/dave/fix-stdout...
2020-04-17 whitequarkMerge pull request #1951 from whitequark/rtlil-string_a...
2020-04-17 David Shahqbfsat: Fix illegal use of 'stdout' identifier
2020-04-17 Alberto GonzalezSet Verilog source location for explicit blocks (`begin...
2020-04-17 Alberto GonzalezAdd Verilog source location information to `AST_POSEDGE...
2020-04-17 whitequarkMerge pull request #1898 from boqwxp/locations
2020-04-17 whitequarkMerge pull request #1864 from boqwxp/cleanup_techmap_abc
2020-04-17 whitequarkMerge pull request #1888 from boqwxp/cleanup_scatter
2020-04-17 whitequarkMerge pull request #1882 from boqwxp/cleanup_rename
2020-04-16 whitequarkMerge pull request #1929 from YosysHQ/eddie/select_unset
2020-04-16 whitequarkrtlil: add AttrObject::has_attribute.
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