2021-12-31 |
Robin Ole Heinemann | *: remove unused variables |
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2021-12-31 |
Robin Ole Heinemann | *: remove unused imports |
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2021-12-31 |
Thomas Watson | tests.hdl.dsl: add tests for mis-nested Switch/Case... |
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2021-12-31 |
Thomas Watson | hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else... |
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2021-12-31 |
Adam Greig | vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll... |
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2021-12-31 |
whitequark | CI: fix sri-csl/formal-methods PPA series. |
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2021-12-31 |
whitequark | hdl.ast: handle int subclasses as slice start/stop... |
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2021-12-31 |
dx-mon | compat.genlib.roundrobin: fix missing imports |
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2021-12-31 |
nickoe | vendor.xilinx_7series: fix tool names for symbiflow. |
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2021-12-31 |
Katherine Temkin | vendor.lattice_ecp5: correctly generate OE signaling... |
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2021-12-31 |
Adam Greig | vendor.lattice_ecp5: replicate OE signal for each outpu... |
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2021-12-31 |
Joel Stanley | docs: Update up_counter to avoid deprecation warning |
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2021-12-31 |
Adam Greig | vendor.lattice_ecp5: remove outdated comment in ECP5... |
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2021-12-31 |
Robin Ole Heinemann | lib.fifo.AsyncFIFOBuffered: fix output register accounting |
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2021-12-31 |
Robin Ole Heinemann | lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency |
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2021-12-31 |
Robin Ole Heinemann | lib.fifo: use proper clock domains in AsyncFIFO tests |
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2021-12-31 |
Robin Ole Heinemann | lib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead... |
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2021-12-31 |
whitequark | Revert "vendor.xilinx_7series: byte swap generated... |
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2021-12-31 |
whitequark | hdl.ast: formatting. NFC. |
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2021-12-31 |
whitequark | hdl.ast: normalize case values to two's complement... |
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2021-12-31 |
whitequark | back.rtlil: give private items an appropriate name... |
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2021-12-31 |
whitequark | build.plat: make `verbose` work like all other overrides. |
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2021-12-31 |
whitequark | vendor.intel: implement `add_settings` (QSF) and `add_c... |
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2021-12-31 |
whitequark | vendor.xilinx_spartan_3_6: fix typo. |
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2021-12-31 |
whitequark | hdl.ast: remove dead code. NFC. |
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2021-12-31 |
awygle | nmigen.hdl.rec: restore Record.shape(). |
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2021-12-31 |
Marcelina Kościelnicka | sim._pyrtl: mask Mux selection operand. |
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2021-12-31 |
Jan Kowalewski | vendor.quicklogic: enable SoC clock configuration |
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2021-12-31 |
whitequark | vendor.quicklogic: write OpenOCD scripts as part of... |
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2021-12-31 |
whitequark | build.plat: TemplatedPlatform.iter_extra_files→Platform... |
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2021-12-31 |
awygle | hdl.rec: proxy operators correctly. |
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2021-12-31 |
Konrad Beckmann | vendor.intel: add support for Cyclone V internal oscillator |
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2021-12-31 |
whitequark | hdl.ast: deprecate UserValue in favor of ValueCastable. |
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2021-12-31 |
whitequark | sim.pysim: avoid redundant VCD updates. |
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2021-12-31 |
whitequark | examples: clean up oudated code. |
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2021-12-31 |
whitequark | Fix commit 8313d6e7. |
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2021-12-31 |
whitequark | cli: update deprecated import. |
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2021-12-31 |
whitequark | CI: add CPython 3.9 to test matrix. |
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2021-12-31 |
whitequark | CI: run testsuite with -Werror. |
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2021-12-31 |
whitequark | vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_... |
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2021-12-31 |
awygle | hdl.rec: migrate Record from UserValue to ValueCastable. |
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2021-12-31 |
awygle | hdl.ast: implement ValueCastable. |
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2021-12-31 |
whitequark | vendor.quicklogic: part→package |
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2021-12-31 |
Norbert Braun | vendor.xilinx_7series: byte swap generated bitstream |
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2021-12-31 |
Jaro Habiger | lib.fifo: fix {r,w}_level in AsyncFIFOBuffered |
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2021-12-31 |
Jaro Habiger | lib.fifo: fix level on fifo full |
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2021-12-31 |
David Lattimore | vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC... |
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2021-12-31 |
Jan Kowalewski | vendor.quicklogic: utilize internal SoC clock in EOS-S3 |
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2021-12-31 |
Jan Kowalewski | vendor.quicklogic: fix toolchain nomenclature |
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2021-12-31 |
Robin Ole Heinemann | lib.fifo.AsyncFFSynchronizer: check input and output... |
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2021-12-31 |
whitequark | build.dsl: clean up inversion logic. |
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2021-12-31 |
whitequark | back.{verilog,rtlil}: adjust $verilog_initial_trigger... |
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2021-12-31 |
whitequark | CI: disable codecov project status. |
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2021-12-31 |
anuejn | lib.fifo.AsyncFIFO: fix incorrect latency of r_level. |
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2021-12-31 |
anuejn | tests: make spec directory name unique per test method. |
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2021-12-31 |
whitequark | sim._pyrtl: sign extend RHS of assignment. |
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2021-12-31 |
whitequark | hdl.dsl: error on Elif immediately nested in an If. |
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2021-12-31 |
Jan Kowalewski | vendor.quicklogic: fix syntax |
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2021-12-31 |
Luke Kenneth... | setup.py: Exclude "tests" package |
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2021-12-31 |
Xiretza | hdl.ir: Update error message for Instance arguments |
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2021-12-31 |
whitequark | README: Quicklogic EOS S3 is now supported. |
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2021-12-31 |
whitequark | CI: fix code coverage collection. |
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2021-12-31 |
Jan Kowalewski | vendor.quicklogic: new platform. |
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2021-12-31 |
whitequark | tests: keep comments up to date. NFC. |
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2021-12-31 |
whitequark | build.plat: avoid type confusion in _check_feature. |
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2021-12-31 |
Jean-François... | hdl.mem: document ReadPort and WritePort. |
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2021-12-31 |
William D.... | vendor.lattice_{ecp5,machxo_2_3l}: explain how to set... |
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2021-12-31 |
whitequark | back.verilog: use `proc -nomux` if it is available. |
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2021-12-31 |
whitequark | sim: split into base, core, and engines. |
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2021-12-31 |
whitequark | sim.pysim: in write_vcd(), close files if an exception... |
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2021-12-31 |
whitequark | sim._pyclock: new type of process. |
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2021-12-31 |
whitequark | sim._pycoro: make src_loc() more robust. |
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2021-12-31 |
whitequark | _toolchain.cxx: work around PyPy missing LDCXXSHARED... |
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2021-12-31 |
whitequark | _toolchain.cxx: new toolchain. |
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2021-12-31 |
whitequark | hdl.ast: clarify exception message for out of bounds... |
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2021-12-31 |
whitequark | nmigen.test.utils: restore FHDLTestCase to gracefully... |
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2021-12-31 |
Luke Kenneth... | remove exclude tests in setup.py |
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2021-12-31 |
whitequark | tests: move out of the main package. |
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2021-12-31 |
Luke Kenneth... | add paramiko extras |
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2021-12-31 |
William D.... | build.run: implement SSH remote builds using Paramiko. |
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2021-12-31 |
whitequark | back.rtlil: do not squash empty modules. |
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2021-12-31 |
whitequark | back.verilog: omit Verilog initial trigger only if... |
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2021-12-31 |
whitequark | vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVIC... |
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2021-12-31 |
whitequark | vendor.xilinx_7series: unbreak. |
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2021-12-31 |
whitequark | sim._pyrtl: optimize uses of reflexive operators. |
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2021-12-31 |
whitequark | back.cxxrtl: actualize Yosys version requirement. |
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2021-12-31 |
whitequark | hdl.ast: avoid unnecessary sign padding in ArrayProxy. |
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2021-12-31 |
whitequark | sim._pyrtl: fix miscompilation of -(Const(0b11, 2)... |
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2021-12-31 |
Luke Kenneth... | lib.cdc: in AsyncFFSynchronizer(), rename domain= to |
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2021-12-31 |
Robin Ole Heinemann | vendor.lattice_machxo_2_3l: add SRAM svf generation |
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2021-12-31 |
Mariusz Glebocki | vendor: Add initial support for Symbiflow for Xilinx... |
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2021-12-31 |
Mariusz Glebocki | vendor.xilinx_7series: add `_part` property getter |
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2021-12-31 |
Xiretza | cli: Improve help texts |
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2021-12-31 |
whitequark | docs/lang: use less confusing placeholder variable... |
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2021-12-31 |
awygle | lib.fifo: add `r_level` and `w_level` to all FIFOs |
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2021-12-31 |
whitequark | Add Linguist tags to .gitattributes. |
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2021-12-31 |
Robin Ole Heinemann | vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir... |
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2021-12-31 |
whitequark | build,vendor: never carry around parts of differential... |
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2021-12-31 |
whitequark | vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather... |
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2021-12-31 |
Adam Greig | hdl.mem: cast reset value for transparent read ports... |
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