yosys.git
2019-07-01 Eddie HungSpace
2019-07-01 Eddie HungMove CHANGELOG entry from yosys-0.8 to 0.9
2019-07-01 Eddie HungMerge branch 'master' into eddie/script_from_wire
2019-07-01 Eddie HungMove abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
2019-07-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-06-30 Eddie Hunginstall *_nowide.lut files
2019-06-28 Eddie HungMerge pull request #1149 from gsomlo/gls-1098-abcext...
2019-06-28 Eddie HungMerge branch 'master' into eddie/script_from_wire
2019-06-28 Eddie Hungautotest.sh to define _AUTOTB when test_autotb
2019-06-28 Eddie HungTry command in another module
2019-06-28 Eddie HungAdd to CHANGELOG
2019-06-28 Eddie HungSupport ability for "script -select" to take commands...
2019-06-28 Eddie HungAdd test
2019-06-28 Eddie HungReplace log_assert() with meaningful log_error()
2019-06-28 Eddie HungRemove peepopt call in synth_xilinx since already in...
2019-06-28 Gabriel L.... Make abc9 pass aware of optional ABCEXTERNAL override
2019-06-28 Eddie HungAdd missing CHANGELOG entries
2019-06-28 Eddie HungFix spacing
2019-06-28 Eddie HungMerge pull request #1098 from YosysHQ/xaig
2019-06-28 Eddie HungAdd generic __builtin_bswap32 function
2019-06-28 Eddie HungAlso fix write_aiger for UB
2019-06-28 Eddie HungFix more potential for undefined behaviour due to conta...
2019-06-28 Eddie HungUpdate synth_ice40 -device doc to be relevant for ...
2019-06-28 Eddie HungDisable boxing of ECP5 dist RAM due to regression
2019-06-28 Eddie HungAdd write address to abc_scc_break of ECP5 dist RAM
2019-06-28 Eddie HungFix DO4 typo
2019-06-28 Clifford WolfMerge pull request #1146 from gsomlo/gls-test-abc-ext
2019-06-28 Clifford WolfMerge pull request #1046 from bogdanvuk/master
2019-06-28 Gabriel L.... tests: use optional ABCEXTERNAL when specified
2019-06-27 Eddie HungReduce diff with upstream
2019-06-27 Eddie HungExtraneous newline
2019-06-27 Eddie HungRemove noise from ice40/cells_sim.v
2019-06-27 Eddie HungRefactor for one "abc_carry" attribute on module
2019-06-27 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-27 Eddie HungDo not use Module::remove() iterator version
2019-06-27 Eddie HungRemove redundant doc
2019-06-27 Eddie HungRemove &retime when abc9 -fast
2019-06-27 Eddie HungCleanup abc9.cc
2019-06-27 Eddie HungUndo iterator based Module::remove() for cells, as...
2019-06-27 Bogdan VukobratovicAdd help for "-sat" option inside opt_rmdff. "opt"...
2019-06-27 Bogdan VukobratovicFix memory leak when one of multiple DFF cells is remov...
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungMerge pull request #1139 from YosysHQ/dave/check-sim...
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungGrr
2019-06-27 Eddie HungCapitalisation
2019-06-27 Eddie HungMake CHANGELOG clearer
2019-06-27 Eddie HungMerge pull request #1143 from YosysHQ/clifford/fix1135
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungAdd warning if synth_xilinx -abc9 with family != xc7
2019-06-27 Eddie HungRemove unneeded include
2019-06-27 Eddie HungMerge origin/master
2019-06-27 Eddie HungAdd simcells.v, simlib.v, and some output
2019-06-27 Eddie HungAdd #1135 testcase
2019-06-27 Eddie Hungsynth_xilinx -arch -> -family, consistent with older...
2019-06-27 Eddie HungMerge pull request #1142 from YosysHQ/clifford/fix1132
2019-06-27 Eddie HungMerge pull request #1138 from YosysHQ/koriakin/xc7nocar...
2019-06-27 Eddie HungCopy tests from eddie/fix1132
2019-06-27 Bogdan VukobratovicMerge remote-tracking branch 'upstream/master'
2019-06-27 Clifford WolfAdd "pmux2shiftx -norange", fixes #1135
2019-06-27 Clifford WolfFix handling of partial covers in muxcover, fixes ...
2019-06-27 Eddie HungFix spacing
2019-06-27 Eddie HungImprove debugging message for comb loops
2019-06-27 Eddie HungAdd WE to ECP5 dist RAM's abc_scc_break too
2019-06-27 Eddie HungUpdate comment on boxes
2019-06-27 Eddie HungAdd "WE" to dist RAM's abc_scc_break
2019-06-27 Eddie HungSupport more than one port in the abc_scc_break attr
2019-06-27 Eddie HungAdd write_xaiger into CHANGELOG
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungGrrr
2019-06-26 David Shahtests: Check that Icarus can parse arch sim models
2019-06-26 Eddie HungRemove unused var
2019-06-26 Eddie HungAdd _nowide variants of LUT libraries in -nowidelut...
2019-06-26 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungFix spacing
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungOops. Actually use nocarry flag as spotted by @koriakin
2019-06-26 Clifford WolfMerge pull request #1137 from mmicko/cell_sim_fix
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Miodrag MilanovicSimulation model verilog fix
2019-06-26 Eddie Hungsynth_ecp5 rename -nomux to -nowidelut, but preserve...
2019-06-26 Eddie HungMerge branch 'xc7nocarrymux' of https://github.com...
2019-06-26 Clifford WolfImprove opt_clean handling of unused public wires
2019-06-26 Eddie HungMerge pull request #1136 from YosysHQ/xaig_ice40_wire_del
2019-06-26 Clifford WolfImprove BTOR2 handling of undriven wires
2019-06-26 David Shahabc9: Add wire delays to synth_ice40
2019-06-26 Clifford WolfFix segfault on failed VERILOG_FRONTEND::const2ast...
2019-06-26 Clifford WolfDo not clean up buffer cells with "keep" attribute...
2019-06-26 Clifford WolfEscape scope names starting with dollar sign in smtio.py
2019-06-26 whitequarkAdd more ECP5 Diamond flip-flops.
2019-06-25 Eddie HungMissing muxpack.o in Makefile
2019-06-25 Eddie HungRealistic delays for RAM32X1D too
2019-06-25 Eddie HungAdd RAM32X1D box info
2019-06-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-25 Eddie HungAdd testcase from #335, fixed by #1130
2019-06-25 Clifford WolfMerge pull request #1130 from YosysHQ/eddie/fix710
2019-06-25 Eddie HungFix spacing
2019-06-25 Eddie HungMove only one consumer check outside of while loop
2019-06-25 Eddie HungMerge pull request #1129 from YosysHQ/eddie/ram32x1d
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