yosys.git
2019-02-20 Eddie Hungabc9 to cope with indexed wires when creating $lut...
2019-02-19 Eddie HungAdd a quick abc9 test
2019-02-19 Eddie HungSame for ascii AIGERs too
2019-02-19 Eddie Hungread_aiger to cope with non-unique POs
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-19 Eddie Hungabc9 to replace $_NOT_ with $lut
2019-02-19 Eddie Hungread_aiger to create sane $lut names, and rename when...
2019-02-19 Eddie HungAdd comment
2019-02-19 Eddie HungGet rid of boost dep, fix the FIXMEs for Win32?
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-17 Eddie HungGet rid of debugging stuff in abc9
2019-02-17 Eddie HungIn read_xaiger, do not construct ConstEval for every LUT
2019-02-17 Eddie HungCleanup
2019-02-17 Eddie Hungread_aiger to ignore output = input of same wire; also...
2019-02-17 Eddie HungCleanup
2019-02-17 Eddie Hungwrite_xaiger to support non-bit cell connections, and...
2019-02-17 Eddie Hungabc9 to write_aiger with -O option, and ignore dummy...
2019-02-17 Eddie Hungwrite_aiger -O to write dummy output as __dummy_o__
2019-02-16 Eddie Hungabc9 to handle comb loops, cope with constant outputs...
2019-02-16 Eddie Hungread_aiger to disable log_debug
2019-02-16 Eddie Hungexpose command to not skip 'internal' wires beginning...
2019-02-16 Eddie Hungread_xaiger() to use f.read() not readsome()
2019-02-16 Eddie Hungabc9 to cope with non-wideports, count cells properly
2019-02-16 Eddie HungTidy up write_xaiger
2019-02-16 Eddie Hungwrite_aiger() to perform CI/CO post-processing and...
2019-02-16 Eddie Hungread_aiger() to cope with constant outputs, mixed widep...
2019-02-15 Eddie HungMove lookup inside if
2019-02-15 Eddie HungFixes needed for DFF circuits
2019-02-15 Eddie HungRefactor
2019-02-15 Eddie HungCope with width != 1 when re-mapping cells
2019-02-15 Jim LawsonRemoved unused variables, functions.
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS
2019-02-15 Eddie Hungabc9 to stitch results with CI/CO properly
2019-02-15 Eddie Hungread_aiger with more asserts, and call clean
2019-02-15 Eddie Hungwrite_xaiger to cope with unknown cells by transforming...
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-14 Eddie HungMore cleanup
2019-02-14 Eddie HungMore cleanup of write_xaiger
2019-02-14 Eddie HungGet rid of formal stuff from xaiger backend
2019-02-14 Eddie Hungsynth_ice40 to have new -abc9 arg
2019-02-14 Eddie HungLeave FIXME for clean
2019-02-14 Eddie HungUse module->addLut()
2019-02-14 Eddie HungFix stitching
2019-02-14 Eddie HungUse ConstEval to compute LUT masks
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-13 Eddie HungRip out some more stuff
2019-02-13 Clifford WolfFix sign handling of real constants
2019-02-13 Eddie HungRip out unused functions in abc9
2019-02-12 Eddie HungAdd support for read_aiger -wideports
2019-02-12 Eddie HungAdd support for read_aiger -map
2019-02-12 Eddie HungParse 'm' in xaiger
2019-02-12 Eddie HungWIP for ABC with aiger
2019-02-12 Eddie HungMissing headers for Xcode?
2019-02-12 Eddie HungMerge branch 'read_aiger' of github.com:eddiehung/yosys...
2019-02-12 Eddie HungUse module->add{Not,And}Gate() functions
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a...
2019-02-12 Clifford WolfMerge pull request #806 from daveshah1/fsm_opt_no_reset
2019-02-11 Eddie HungAdd read_xaiger
2019-02-11 Eddie HungAdd write_xaiger
2019-02-11 Eddie HungDo not break for constraints
2019-02-11 Eddie HungNo increment line_count for binary ANDs
2019-02-11 Eddie HungDo not ignore newline after AND in binary AIG
2019-02-08 Eddie HungCopy backends/aiger/aiger.cc to xaiger.cc
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-08 Eddie HungCompile abc9
2019-02-08 Eddie HungRefactor kernel/cost.h definition into cost.cc
2019-02-08 Eddie HungCopy abc.cc to abc9.cc
2019-02-08 Eddie HungaddDff -> addDffGate as per @daveshah1
2019-02-08 Eddie HungFix tabulation
2019-02-08 Eddie Hung-module_name arg to go before -clk_name
2019-02-08 Eddie HungSupport and differentiate between ASCII and binary...
2019-02-08 Eddie HungAdd missing "[options]" to read_blif help
2019-02-08 Eddie HungAllow module name to be determined by argument too
2019-02-08 Eddie HungRefactor into AigerReader class
2019-02-08 Eddie HungParse binary AIG files
2019-02-08 Eddie HungAdd binary AIGs converted from AAG
2019-02-08 Eddie HungRefactor to parse_aiger_header()
2019-02-08 Eddie HungAdd comment
2019-02-08 Eddie HungHandle reset logic in latches
2019-02-08 Eddie HungChange literal vars from int to unsigned
2019-02-08 Eddie HungCreate clk outside of latch loop
2019-02-08 Eddie HungHandle latch symbols too
2019-02-08 Eddie HungRemove return after log_error
2019-02-08 Eddie HungAdd support for symbol tables
2019-02-08 Eddie HungStub for binary AIGER
2019-02-07 David Shahfsm_opt: Fix runtime error for FSMs without a reset...
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie HungRemove check for cell->name[0] == '$'
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRevert most of autotest.sh; for non *.v use Yosys to...
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells
2019-02-06 Eddie HungAdd tests for simple cases using defparam
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