yosys.git
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungCleanup
2019-11-27 Eddie HungCheck for nullptr
2019-11-27 Eddie HungStray log_dump
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungPromote output wires in sigmap so that can be detected
2019-11-27 Eddie HungFix wire width
2019-11-27 Eddie HungFix submod -hidden
2019-11-27 Eddie HungAdd -hidden option to submod
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-26 Eddie HungMove 'clean' from map_luts to finalize
2019-11-26 Eddie HungFix submod -hidden
2019-11-26 Eddie Hungclkpart to use 'submod -hidden'
2019-11-26 Eddie HungAdd -hidden option to submod
2019-11-26 Eddie HungUpdate docs with bullet points
2019-11-26 Eddie HungMove \init from source wire to submod if output port
2019-11-26 Eddie HungAdd testcase where \init is copied
2019-11-25 Eddie HungFold loop
2019-11-25 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-25 Eddie HungFix debug
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Eddie HungSpecial abc9_clock wire to contain only clock signal
2019-11-25 Eddie Hungabc9 to contain time call
2019-11-25 Eddie Hungabc9 to no longer to clock partitioning, operate on...
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMore oopsies
2019-11-23 Eddie HungConditioning abc9 on POs not accurate due to cells
2019-11-23 Eddie HungFor abc9, run clkpart before ff_map and after abc9
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungPrint ".en=" only if there is an enable signal
2019-11-23 Eddie HungEscape IdStrings
2019-11-23 Eddie HungMore sane naming of submod
2019-11-23 Eddie HungAdd -set_attr option, -unpart to take attr name
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
2019-11-23 Eddie HungDo not use log_signal() for empty SigSpec to prevent...
2019-11-23 Eddie HungCall submod once, more meaningful submod names, ignore...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungRemove redundant flatten
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes...
2019-11-23 Eddie Hungsubmod to bitty rather bussy, for bussy wires used...
2019-11-23 Eddie HungStray dump
2019-11-23 Eddie HungMove clkpart into passes/hierarchy
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungConstant driven signals are also an input to submodules
2019-11-23 Eddie HungAdd another test with constant driver
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungOops
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungOnly action if there is more than one clock domain
2019-11-23 Eddie HungReplace TODO
2019-11-23 Eddie HungAdd testcase for signal used as part input part output
2019-11-23 Eddie Hungwrite_xaiger back to working with whole modules only
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungCleanup spacing
2019-11-23 Eddie Hungsigmap(wire) should inherit port_output status of POs
2019-11-23 Eddie HungAdd testcase
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungBrackets
2019-11-22 Eddie HungEntry in Makefile.inc
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungAdd to CHANGELOG
2019-11-22 Eddie HungNew 'clkpart' to {,un}partition design according to...
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-22 Eddie HungRevert "write_xaiger to not use module POs but only...
2019-11-22 Eddie HungMissing endmodule
2019-11-22 Clifford WolfMerge pull request #1517 from YosysHQ/clifford/optmem
2019-11-22 Clifford WolfMerge pull request #1515 from YosysHQ/clifford/svastuff
2019-11-22 Clifford WolfAdd "opt_mem" pass
2019-11-22 Clifford WolfAdd Verific support for SVA nexttime properties
2019-11-22 Clifford WolfImprove handling of verific primitives in "verific...
2019-11-22 Clifford WolfAdd Verific SVA support for "always" properties
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-22 David ShahUpdate CHANGELOG and README
2019-11-22 Eddie HungAnother sloppy mistake!
2019-11-22 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-11-22 Eddie Hungasync2sync -> clk2fflogic
2019-11-22 Eddie Hungwrite_xaiger to not use module POs but only write outpu...
2019-11-22 Eddie HungWhen expanding upwards, do not capture $__ABC9_{FF...
2019-11-22 Eddie HungMerge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-22 Eddie HungAdd test
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-21 David Shahproc_dlatch: Add error handling for incorrect always_...
2019-11-21 David Shahsv: Correct parsing of always_comb, always_ff and alway...
2019-11-20 Eddie HungConsistent log message, ignore 's' extension
2019-11-20 Eddie Hungendomain -> ctrldomain
2019-11-20 Eddie HungAdd blackbox model for $__ABC9_FF_ so that clock partit...
2019-11-20 Eddie HungAdd multi clock test
2019-11-20 Eddie HungFix INIT values
2019-11-20 Clifford WolfMerge pull request #1507 from YosysHQ/clifford/verificfixes
2019-11-20 Clifford WolfCorrectly treat empty modules as blackboxes in Verific
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