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gem5.git
2013-01-05
Gabe Black
SPARC: Keep a copy of the current ASI in the decoder.
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2013-01-05
Gabe Black
ARM: Keep a copy of the fpscr len and stride fields...
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2012-12-30
Nilay Vaish
x86 regressions: stats update due to new x87 instructions
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2012-12-30
Nilay Vaish
x86: implement x87 fp instruction fnstsw
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2012-12-30
Nilay Vaish
x86: implement x87 fp instruction fsincos
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2012-12-12
Nilay Vaish
arm regressions: updates to config.ini, terminal files
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2012-12-12
Nathanael Premillieu
arm: set uopSet_uop as conditional or unconditional...
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2012-12-12
Nathanael Premillieu
arm: set movret_uop as conditional or unconditional...
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2012-12-11
Nilay Vaish
regressions: stats update due to stats from ruby prefetcher
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2012-12-11
Nilay Vaish
ruby: add support for prefetching to MESI protocol
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2012-12-11
Nilay Vaish
ruby: modify the directed tester to read/write streams
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2012-12-11
Nilay Vaish
ruby: change slicc to allow for constructor args
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2012-12-11
Nilay Vaish
ruby: add a prefetcher
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2012-12-11
Nilay Vaish
ruby: add functions for computing next stride/page...
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2012-12-06
Nilay Vaish
regression test: update a couple of config.ini files
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2012-12-06
Erik Tomusk
TournamentBP: Fix some bugs with table sizes and counters
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2012-12-06
Malek Musleh
inorder cpu: add missing DPRINTF argument
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2012-12-06
Nathanael Premillieu
o3 cpu: remove some unused buggy functions in the lsq
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2012-11-19
Andreas Hansson
config: Fix description of checkpoint option from cycle...
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2012-11-16
Nilay Vaish
sim: have a curTick per eventq
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2012-11-10
Nilay Vaish
regressions: stats update due to ruby functional access...
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2012-11-10
Nilay Vaish
ruby: support functional accesses in garnet flexible...
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2012-11-10
Nilay Vaish
ruby: bug in functionalRead, revert recent changes
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2012-11-08
Andreas Hansson
mem: Fix DRAM draining to ensure write queue is empty
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2012-11-03
Lluis Vilanova
x86, util: add m5_writefile to m5op_x86.S
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2012-11-02
Hamid Reza...
ruby: reset and dump stats along with reset of the...
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2012-11-02
Ali Saidi
mem: fix use after free issue in memories until 4-phase...
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2012-11-02
Ali Saidi
update stats for preceeding changes
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2012-11-02
Andreas Sandberg
mem: Add support for writing back and flushing caches
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2012-11-02
Andreas Sandberg
sim: Add drain methods to request additional cleanup...
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2012-11-02
Andreas Sandberg
sim: Add SWIG interface for Serializable
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2012-11-02
Andreas Sandberg
python: Rename doDrain()->drain() and make it do the...
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2012-11-02
Andreas Sandberg
sim: Reuse the code to change memory mode.
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2012-11-02
Andreas Sandberg
sim: Move the draining interface into a separate base...
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2012-11-02
Andreas Sandberg
cpu: O3 add a header declaring the DerivO3CPU
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2012-11-02
Andreas Sandberg
cpu: Add header files for checker CPUs
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2012-11-02
Andreas Sandberg
dev: Fix ethernet device inheritance structure
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2012-11-02
Andreas Sandberg
sim: Include object header files in SWIG interfaces
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2012-11-02
Andreas Sandberg
pci: Make Python wrapper cast to the right type
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2012-11-02
Andreas Sandberg
mips: Remove unused Python file
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2012-11-02
Andreas Sandberg
dev: Add missing inline declarations
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2012-11-02
Andreas Sandberg
base: Add missing header file to addr_range.hh.
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2012-10-09
James Clarkson
m5: Expose m5 pseudo-instructions to C/C++ via a static...
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2012-11-02
Dam Sunwoo
ARM: dump stats and process info on context switches
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2012-11-02
Chander Sudanthi
base: Fix a few incorrectly handled print format cases
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2012-11-02
Chander Sudanthi
base: split out the VncServer into a VncInput and Serve...
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2012-11-02
Dam Sunwoo
ISA: generic Linux thread info support
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2012-11-02
Ali Saidi
sim: Fix as issue where exit events on instr queues...
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2012-11-02
Mrinmoy Ghosh
o3: Fix a couple of issues with the local predictor.
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2012-11-02
Andreas Sandberg
Partly revert [4f54b0f229b5] and move draining to m5...
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2012-10-31
Andreas Hansson
mem: Fix typo in port comments
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2012-10-31
Andreas Hansson
stats: Update stats for fixed simple-atomic-mp config
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2012-10-31
Andreas Hansson
config: Fix a typo in the simple-atomic-mp configuration
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2012-10-30
Andreas Hansson
stats: Update stats for unified cache configuration
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2012-10-30
Andreas Hansson
config: Unify caches used in regressions and adjust...
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2012-10-27
Nilay Vaish
regressions: update stats for ruby fs test
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2012-10-27
Malek Musleh
ruby: set the is_icache param for caches
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2012-10-27
Jason Power...
Ruby: Use block size in configuring directory bits...
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2012-10-26
Andreas Hansson
config: Add a check for fastmem only used with Atomic CPU
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2012-10-26
Andreas Hansson
config: Remove unused mem_size in fs.py
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2012-10-26
Andreas Hansson
config: Fix the cache class naming in regression scripts
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2012-10-25
Andreas Hansson
stats: Update the stats to reflect the 1GHz default...
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2012-10-25
Andreas Hansson
dev: Make default clock more reasonable for system...
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2012-10-25
Andreas Hansson
stats: Update stats to reflect use of SimpleDRAM
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2012-10-25
Andreas Hansson
config: Use SimpleDRAM in full-system, and with o3...
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2012-10-25
Andreas Hansson
config: Use shared cache config for regressions
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2012-10-25
Andreas Hansson
arm: Use table walker clock that is inherited from CPU
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2012-10-23
Andreas Hansson
stats: Update stats for DMA port send
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2012-10-23
Andreas Hansson
dev: Remove zero-time loop in DMA timing send
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2012-10-23
Andreas Hansson
stats: Update t1000 stats to match recent changes
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2012-10-18
Nilay Vaish
ruby: functional access updates to network test protocol
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2012-10-16
Nilay Vaish
regressions: update stats for eio tests
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2012-10-16
Nilay Vaish
regressions: update stats due to change to ruby memory...
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2012-10-15
Nilay Vaish
ruby: improved support for functional accesses
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2012-10-15
Nilay Vaish
memtest: move check on outstanding requests
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2012-10-15
Nilay Vaish
ruby: register multiple memory controllers
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2012-10-15
Nilay Vaish
ruby: remove AbstractMemOrCache
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2012-10-15
Nilay Vaish
ruby: allow function definition in slicc structs
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2012-10-15
Nilay Vaish
ruby banked array: do away with event scheduling
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2012-10-15
Nilay Vaish
ruby: reset timing after cache warm up
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2012-10-15
Andreas Hansson
Mem: Fix incorrect logic in bus blocksize check
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2012-10-15
Andreas Hansson
Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15
Andreas Hansson
Mem: Separate the host and guest views of memory backin...
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2012-10-15
Andreas Hansson
Checkpoint: Make system serialize call children
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2012-10-15
Andreas Hansson
Mem: Use deque instead of list for bus retries
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2012-10-15
Andreas Hansson
Fix: Address a few minor issues identified by cppcheck
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2012-10-15
Andreas Hansson
Stats: Update stats for cache timings in cycles
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2012-10-15
Andreas Hansson
Mem: Use cycles to express cache-related latencies
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2012-10-15
Andreas Hansson
Stats: Update memtest stats after setting clock
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2012-10-15
Andreas Hansson
Configs: Set the memtest clock to a reasonable value
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2012-10-15
Andreas Hansson
Stats: Update stats for new default L1-to-L2 bus clock...
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2012-10-15
Andreas Hansson
Regression: Use CPU clock and 32-byte width for L1...
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2012-10-15
Andreas Hansson
Stats: Update stats for use of two-level builder
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2012-10-15
Andreas Hansson
Regression: Use addTwoLevelCacheHierarchy in configs
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2012-10-15
Andreas Hansson
Clock: Inherit the clock from parent by default
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2012-10-15
Andreas Hansson
Param: Fix proxy traversal to support chained proxies
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2012-10-15
Andreas Hansson
Mem: Use range operations in bus in preparation for...
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2012-10-11
Andreas Hansson
Mem: Determine bus block size during initialisation
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2012-10-11
Andreas Hansson
Doxygen: Update the version of the Doxyfile
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2012-10-02
Nilay Vaish
Regression Tests: Update statistics
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