gem5.git
2017-10-13 Nikos Nikoleriscpu-o3: Check predication before the SQ size for a...
2017-10-13 Nikos Nikoleriscpu-o3: Avoid early checker verification for store...
2017-10-05 Curtis Dunhamtests: Fix path for module imports in ARM system config...
2017-10-05 Gabe Blackmisc: Add util/packet_pb2.py to .gitignore.
2017-10-05 Gabe Blackmisc: Use a Makefile to ensure util/packet_pb2.py is...
2017-10-05 Gabe Blackmisc: When building packet_pb2.py, don't assume a parti...
2017-10-05 Gabe Blackmisc: Make decode_packet_trace.py print the new master...
2017-10-05 Gabe Blackmisc: Small style fix in _EncodeVarint32.
2017-10-05 Gabe Blackmisc: Rename the (De|En)codeVarint function _(De|En...
2017-10-05 Gabe Blackmisc: Fix the indentation in DecodeVarint in util/proto...
2017-10-04 Matthias Jungtlm: Elastic Trace Example with L2 Cache Added
2017-09-28 Rico Amslingersim-se: Fix mremap for downward growing mmap regions
2017-09-27 Bjoern A. Zeebarch-x86: fix CondInst decoding for MOV to Control...
2017-09-27 Bjoern A. Zeebarch: change panic for Vector traceData to warn_once
2017-09-27 Bjoern A. Zeebsim: make compile on FreeBSD prior to 11
2017-09-26 Gabe Blackutil: Make dot_writer ignore NULL simobjects.
2017-09-26 Gabe Blackdev: Make the IDE controller handle NULL simobject...
2017-09-26 Gabe Blacksim: Add a get_config_as_dict to the NullSimObject...
2017-09-26 Gabe Blacksim: Don't add the NULL SimObject as a child of other...
2017-09-26 Gabe Blackmisc: Make the m5 utilities writefile command accept...
2017-09-26 Gabe Blacksim: Give the NullSimObject singleton a _name.
2017-09-26 Gabe Blacksim: Add a NullSimObject.descendants function.
2017-09-26 Gabe Blacksim: Add a clear_parent function to NullSimObject.
2017-09-26 Gabe Blacksim: Check the SimObjectVector.has_parent function...
2017-09-26 Gabe Blacksim: Only consider non-NULL elements in SimObjectVector...
2017-09-26 Gabe Blacksim: Add a set_parent to NullSimObject which does nothing.
2017-09-25 Gabe Blackmem: Fill the new packet ID fields with master IDs...
2017-09-25 Gabe Blackmem: Add a "map" of packet IDs to strings in probe...
2017-09-25 Gabe Blackmem: Trace the request master ID in the MemTraceProbe.
2017-09-25 Gabe Blackmem: Record the request master ID in the PacketInfo...
2017-09-25 Anouk Van Laerdev, virtio: Improvements to diod process handling
2017-09-21 Gabe Blackalpha: Move some initialization logic from loadState...
2017-09-21 Gabe Blacksim: Stop using loadState in the Root SimObject.
2017-09-20 Gabe Blackkvm: arm: Get rid of functions which just wrap the...
2017-09-11 Matthias Jungtlm: Don't set SystemC time resolution
2017-09-11 Gabe Blackstats: Move the swpipl function into the Alpha kernel...
2017-09-11 Gabe Blackstats: Get rid of some kernel stats related cruft.
2017-09-06 Rico Amslingercpu: Fix bi-mode branch predictor thresholds
2017-09-01 Pau Cabrecpu-minor: Fix for addr range coverage calculation
2017-08-31 Paul Rosenfeldscons: bump required python version to 2.7 to support...
2017-08-30 Jose Marinhoarch-arm: Only increment SW PMU counters on writes...
2017-08-30 Andreas Sandbergarch-arm: Add missing override keywords in fault.hh
2017-08-30 Andreas Sandbergarch-x86: Add missing override in the X86 TLB
2017-08-30 Andreas Sandbergarch-sparc: Add a FaultVals instantiation for VecDisabled
2017-08-30 Andreas Sandbergarch-alpha: Add missing overrides
2017-08-30 Andreas Sandbergpython: Make GlobalExitEvent.getCode() return an int
2017-08-30 Matthias Hillecpu-o3: fix data pkt initialization for split load
2017-08-28 Gabe Blackx86: Use the new CondInst format for moves to/from...
2017-08-28 Gabe Blackx86: Add a "CondInst" format for conditionally decoded...
2017-08-12 Gabe Blackdev: Fix an IDE error check.
2017-08-08 Pau Cabremem-cache: Delete squashed HWPrefetches
2017-08-03 Andreas Sandbergconfigs, arm: Fix incorrect use of mem_range in bL...
2017-08-03 Andreas Sandbergarm, config: Fix CPU names in ARM example configs
2017-08-02 Gabe Blackbase: Give more information when setting up asynchronou...
2017-08-01 Éder F. Zulianmisc: git ignore file udpated
2017-08-01 Andreas Sandbergstyle: Add shared gem5 headers to the style checker
2017-08-01 Andreas Sandbergutil: Move m5op.h to the shared include directory
2017-08-01 Andreas Sandbergutil, m5: Use consistent naming for m5op C symbols
2017-08-01 Andreas Sandbergarch-arm: Use named constants for m5op instructions
2017-08-01 Andreas Sandbergsim: Use named constants for pseudo ops
2017-08-01 Andreas Sandbergutil: Move the m5ops.h file to a shared directory
2017-08-01 Andreas Sandbergkvm, arm: Switch to the device EQ when accessing ISA...
2017-08-01 Andreas Sandbergkvm: Add a helper method to access device event queues
2017-08-01 Andreas Sandbergcpu, kvm: Fix deadlock issue when resuming a drained...
2017-08-01 Andreas Sandbergarch-arm: Switch to DTOnly as the default machine type
2017-07-28 Andreas Sandbergconfig: Discover CPU timing models based on target ISA
2017-07-27 Gabor Dozsaconfig, arm: SE configuration for the ARM starter kit
2017-07-27 Gabor Dozsaconfig, arm: FS configuration for the ARM starter kit
2017-07-27 Ashkan Tousiconfig, arm: Add a high-performance in order timing...
2017-07-27 Gabor Dozsaconfig: Change mem_range attribute naming in ARM Simple...
2017-07-25 Nikos Nikoleristests: Fix path for module imports in ARM system configs
2017-07-25 Pau Cabreconfigs,sim-se: fix se.py multi-cpu multi-cmd issue
2017-07-20 Jose Marinhosim: Prevent segfault in the wakeCpu m5op if id is...
2017-07-19 Rekai Gonzalez... cpu: Add missing rename of vector registers in the...
2017-07-17 Anouk Van Laercpu,o3: Fixed checkpointing bug occuring in the o3 CPU
2017-07-17 Andreas Sandbergtests: Don't treat new stats as a cause for failures
2017-07-17 Sean Wilsonsim, x86: Make clone a virtual function
2017-07-17 Swapnil Hariax86: Add stats to X86 TLB
2017-07-17 Alec Roelkeriscv: Define register index constants using literals
2017-07-14 Gabe Blackriscv: Disambiguate between the C and C++ versions...
2017-07-14 Alec Roelketests: Upate RISC-V binaries and results
2017-07-14 Alec Roelkeriscv: Fix bugs with RISC-V decoder and detailed CPUs
2017-07-14 Alec Roelkeriscv: Add unused attribute to some registers.hh constants
2017-07-13 Gedare Bloomarch-arm: fix ldm of pc interswitching branch
2017-07-12 Sean Wilsonruby: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsonarm: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsondev: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsonnet: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsontesters: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsonkvm, mem: Refactor some Event subclasses into lambdas
2017-07-12 Sean Wilsoncpu: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsongpu-compute: Refactor some Event subclasses to lambdas
2017-07-12 Sean Wilsonsim, gdb: Refactor some Event subclasses into lambdas
2017-07-12 Sean Wilsonmips, x86: Refactor some Event subclasses into lambdas
2017-07-12 Pau Cabreutil,arch-arm: Added python script to generate ARM...
2017-07-12 Jose Marinhocpu, sim: Add param to force CPUs to wait for GDB
2017-07-11 Alec Roelkearch-riscv,tests: Add insttests for RV64C
2017-07-11 Alec Roelkearch-riscv: Add support for compressed extension RV64C
2017-07-11 Alec Roelkearch-riscv: Restructure ISA description
2017-07-10 Jose Marinhodev-arm: Add ID registers to the GIC model
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