riscv-isa-sim.git
2010-09-09 Andrew Waterman[pk, sim] added interrupt support to sim; added timer...
2010-09-08 Yunsup Lee[sim] change applink for tohost/fromhost (forgot one...
2010-09-08 Yunsup Lee[sim] change applink for tohost/fromhost
2010-09-07 Andrew Waterman[xcc, sim] added slei/sleui in lieu of slti/sltiu
2010-09-07 Yunsup Lee[sim] yet another fix stdint.h __STDC_LIMIT_MACROS...
2010-09-07 Yunsup Lee[sim] fix stdint.h __STDC_LIMIT_MACROS problem
2010-09-07 Andrew Waterman[sim, xcc] branches now have 2-byte-aligned displacements
2010-09-07 Andrew Waterman[sim, xcc] added PCRs to replace k0 and k1
2010-09-07 Andrew Waterman[sim, xcc] bthread threading model exposed; insn encodi...
2010-09-07 Andrew Waterman[sim] fixed bug in msub.d; added ability to print FPRs...
2010-09-06 Andrew Waterman[sim] added atomic memory operations
2010-08-24 Andrew Waterman[xcc] argc/argv work for 32b programs
2010-08-24 Andrew Waterman[sim] privileged mode support for 32-bit operation
2010-08-23 Andrew Waterman[xcc,sim] added fused multiply-add and its cousins
2010-08-23 Andrew Waterman[xcc,sim] Eliminated slori instruction
2010-08-19 Andrew Waterman[pk,fesvr] improved proxykernel build system
2010-08-18 Andrew Waterman[sim] integrated SoftFloat-3 with ISA sim; removed...
2010-08-18 Andrew Waterman[sim] specialized softfloat for riscv
2010-08-18 Andrew Waterman[sim] added riscv folder to softfloat
2010-08-18 Andrew Waterman[sim] added SoftFloat-3 source
2010-08-10 Andrew Waterman[xcc,sim] implement FP using softfloat
2010-08-10 Andrew Waterman[sim] removed unused elf loader
2010-08-09 Andrew Waterman[sim] added softfloat
2010-08-06 Andrew Waterman[sim,xcc] Added first few Hauser FP insns (sign-injection)
2010-08-05 Andrew Waterman[sim] Bug fixes in shifts, plus a new test case
2010-08-05 Andrew Waterman[xcc] Removed ctc1, cfc1 instructions; added fp move...
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-08-04 Andrew Waterman[sim,xcc] removed sll32/srl32/sra32 opcodes
2010-08-04 Andrew Waterman[pk,sim,xcc] Renamed instructions to RISC-V spec
2010-07-29 Andrew Waterman[gcc] generate code for complex branches
2010-07-29 Andrew Waterman[sim,xcc] Changed instruction format to RISC-V
2010-07-23 Yunsup Lee[sim] various fixes to get the sim work with the fesvr
2010-07-22 Andrew Waterman[pk,sim] removed cop0 console i/o support
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-20 Andrew Waterman[pk,sim] added temporary "exit" functionality
2010-07-19 Andrew WatermanReorganized directory structure