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microwatt.git
2020-07-07
Anton Blanchard
Merge pull request #209 from mikey/yosys
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2020-07-02
Michael Neuling
Add yosys/nextpnr ecp5 and verilog build to CI
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2020-07-02
Michael Neuling
Add FPGA_TARGET=ECP5-EVN make option for synthesis...
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2020-07-02
Michael Neuling
Add SYNTH_ECP5_FLAGS option for building
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2020-07-02
Michael Neuling
Add ram file to synthesis build dependencies
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2020-07-02
Michael Neuling
Add uart16550 files to yosys/nextpnr build
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2020-07-02
Michael Neuling
Add uart16550 files from fusesoc
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2020-07-02
Michael Neuling
Build to tmp file so nextpnr errors don't confuse make
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2020-07-02
Michael Neuling
Fix building with yosys/nextpnr
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2020-07-02
Michael Neuling
Add yosys builds files to gitignore
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2020-07-02
Michael Neuling
Send line feed if we get a carriage return in hello...
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2020-06-30
Michael Neuling
Merge pull request #216 from paulusmack/cfar
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2020-06-30
Paul Mackerras
Merge pull request #206 from Jbalkind/icachecleanup
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2020-06-29
Paul Mackerras
execute1: Do forwarding of the CR result to the next...
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2020-06-29
Paul Mackerras
execute1: Add latch to redirect path
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2020-06-29
Paul Mackerras
logical: Only do output inversion for OP_AND, OP_OR...
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2020-06-29
Paul Mackerras
core: Implement CFAR register
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2020-06-29
Michael Neuling
Merge pull request #213 from ozbenh/uart16550
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2020-06-29
Michael Neuling
Merge pull request #212 from ozbenh/liteeth
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2020-06-29
Michael Neuling
Merge pull request #214 from shingarov/fix-ld-target
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2020-06-26
Boris Shingarov
Fix ld error in elf maketarget
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2020-06-25
Benjamin Herrenschmidt
tests: Add updated micropython build with 16550 support
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2020-06-25
Benjamin Herrenschmidt
sim_console: Fix polling to check for POLLIN
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2020-06-25
Benjamin Herrenschmidt
uart: Make 16550 the default
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2020-06-23
Benjamin Herrenschmidt
syscon: Add flag to indicate the timebase frequency
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2020-06-23
Benjamin Herrenschmidt
console: Add support for the 16550 UART
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2020-06-23
Benjamin Herrenschmidt
uart: Add a simulation model for the 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
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2020-06-23
Benjamin Herrenschmidt
console: Cleanup console API
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2020-06-23
Benjamin Herrenschmidt
uart: Import and hook up opencore 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
ex1: Add SPR_TBU support
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2020-06-23
Benjamin Herrenschmidt
liteeth: Hook up LiteX LiteEth ethernet controller
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2020-06-23
Michael Neuling
Merge pull request #211 from shenki/spi-constraint
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2020-06-23
Joel Stanley
spi: Fix dat_i_l constraints
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2020-06-23
Michael Neuling
Merge pull request #210 from ozbenh/xics
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2020-06-22
Benjamin Herrenschmidt
xics: Add support for reduced priority field size
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2020-06-19
Benjamin Herrenschmidt
xics: Add simple ICS
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2020-06-19
Benjamin Herrenschmidt
xics/icp: MFRR starts at 0xff not 0x00
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2020-06-19
Benjamin Herrenschmidt
tests/xics: Ensure no compiler optimisations in delay()
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2020-06-19
Benjamin Herrenschmidt
xics: ICP should be big endian !
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2020-06-19
Benjamin Herrenschmidt
tests: Fix Makefile.test to not allow host includes
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2020-06-19
Michael Neuling
Merge pull request #208 from paulusmack/faster
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2020-06-17
Paul Mackerras
Merge pull request #207 from ozbenh/misc
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2020-06-16
Paul Mackerras
fpga: Add a xilinx_specific fileset to microwatt.core
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2020-06-16
Paul Mackerras
Make LOG_LENGTH configurable per FPGA variant
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2020-06-15
Paul Mackerras
execute1: Reduce width of the result mux to help timing
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2020-06-15
Paul Mackerras
core: Implement a simple branch predictor
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2020-06-15
Paul Mackerras
decode1: Improve timing for slow SPR decode path
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2020-06-14
Paul Mackerras
decode1: Add a stash buffer to the output
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2020-06-14
Benjamin Herrenschmidt
soc: Slight cleanup of IRQ assignments
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2020-06-14
Benjamin Herrenschmidt
soc: Rename uart_dat8 to uart0_dat8
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2020-06-14
Benjamin Herrenschmidt
soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
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2020-06-13
Jonathan Balkind
Minor refactor of icache to make less dependent on...
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2020-06-13
Paul Mackerras
dcache: Reduce back-to-back store latency from 3 cycles...
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2020-06-13
Benjamin Herrenschmidt
soc: Don't require dram wishbones signals to be wired...
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2020-06-13
Benjamin Herrenschmidt
soc: Add defaults for some input signals
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2020-06-13
Benjamin Herrenschmidt
soc: Remove unused RESET_LOW generic
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2020-06-13
Paul Mackerras
mmu: Take an extra cycle to do TLB invalidations
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2020-06-13
Paul Mackerras
dcache: Reduce latencies and improve timing
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2020-06-13
Paul Mackerras
decode: Work out ispr1/ispr2 in parallel with decode...
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2020-06-13
Paul Mackerras
loadstore1: Reduce busy cycles
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2020-06-13
Paul Mackerras
loadstore1: Complete mfspr/mtspr a cycle later
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2020-06-13
Paul Mackerras
core: Use a busy signal rather than a stall
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2020-06-13
Paul Mackerras
icache: Improve latencies when reloading cache lines
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2020-06-13
Paul Mackerras
multiply: Use DSP48 slices for multiplication on Xilinx...
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2020-06-13
Paul Mackerras
multiply: Move selection of result bits into execute1
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2020-06-13
Paul Mackerras
core: Double the dcache and icache sizes
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2020-06-13
Paul Mackerras
core: Remove fetch2 pipeline stage
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2020-06-13
Paul Mackerras
Add core logging
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2020-06-13
Paul Mackerras
scripts/mw_debug: Make progress counts display on one...
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2020-06-13
Paul Mackerras
tests/xics: Fix assumption that interrupts happen immed...
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2020-06-13
Paul Mackerras
register_file: Report value being written before assert...
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2020-06-13
Paul Mackerras
Merge pull request #205 from ozbenh/timing
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2020-06-13
Paul Mackerras
Merge pull request #204 from ozbenh/spi
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2020-06-13
Benjamin Herrenschmidt
syscon: Remove combinational loop on ack and stall
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2020-06-13
Benjamin Herrenschmidt
bram: Remove combinational loop on stall
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2020-06-13
Benjamin Herrenschmidt
uart: Remove combinational loops on ack and stall signal
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2020-06-13
Benjamin Herrenschmidt
spi: Add booting from flash to litedram init
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2020-06-13
Benjamin Herrenschmidt
spi: Add simulation support
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2020-06-12
Dan Horák
flash-arty: update error message (#203)
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2020-06-12
Benjamin Herrenschmidt
dmi: Add ASYNC_REG attribute on synchronizers (#200)
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2020-06-12
Benjamin Herrenschmidt
icache: Latch PLRU victim output (#199)
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2020-06-12
Paul Mackerras
Merge pull request #198 from ozbenh/litedram
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2020-06-12
Benjamin Herrenschmidt
spi: Add SPI Flash controller
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2020-06-12
Benjamin Herrenschmidt
litedram: L2 use latched refill_index
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2020-06-12
Benjamin Herrenschmidt
litedram: Pipeline store acks in L2
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2020-06-12
Benjamin Herrenschmidt
arty/nexys-video: Update XDC
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2020-06-12
Benjamin Herrenschmidt
litedram: Add stash buffer to the L2 cache wishbone...
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2020-06-12
Benjamin Herrenschmidt
litedram: Defer clearing of tags & valids to improve...
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2020-06-12
Benjamin Herrenschmidt
litedram: Improve dram_tb error output
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2020-06-12
Anton Blanchard
Merge pull request #201 from mikey/github-actions
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2020-06-11
Michael Neuling
Move from travis to github workflow
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2020-06-10
Paul Mackerras
Merge pull request #194 from ozbenh/misc
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2020-06-10
Benjamin Herrenschmidt
gitignore: Add more exlusions
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2020-06-10
Benjamin Herrenschmidt
litedram: Fix DRAM init mem using too many address...
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2020-06-10
Benjamin Herrenschmidt
litedram: Remove remnants of riscv-inits
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2020-06-10
Benjamin Herrenschmidt
mw_debug: Add "save" function to save memory to a file
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2020-06-10
Benjamin Herrenschmidt
sw: Properly mask syscon register fields
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2020-06-09
Michael Neuling
Merge pull request #196 from ozbenh/makefile-lib-fix
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2020-06-09
Michael Neuling
Merge pull request #195 from shenki/nexys-video
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