microwatt.git
2020-07-07 Anton BlanchardMerge pull request #209 from mikey/yosys
2020-07-02 Michael NeulingAdd yosys/nextpnr ecp5 and verilog build to CI
2020-07-02 Michael NeulingAdd FPGA_TARGET=ECP5-EVN make option for synthesis...
2020-07-02 Michael NeulingAdd SYNTH_ECP5_FLAGS option for building
2020-07-02 Michael NeulingAdd ram file to synthesis build dependencies
2020-07-02 Michael NeulingAdd uart16550 files to yosys/nextpnr build
2020-07-02 Michael NeulingAdd uart16550 files from fusesoc
2020-07-02 Michael NeulingBuild to tmp file so nextpnr errors don't confuse make
2020-07-02 Michael NeulingFix building with yosys/nextpnr
2020-07-02 Michael NeulingAdd yosys builds files to gitignore
2020-07-02 Michael NeulingSend line feed if we get a carriage return in hello...
2020-06-30 Michael NeulingMerge pull request #216 from paulusmack/cfar
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Paul Mackerrasexecute1: Do forwarding of the CR result to the next...
2020-06-29 Paul Mackerrasexecute1: Add latch to redirect path
2020-06-29 Paul Mackerraslogical: Only do output inversion for OP_AND, OP_OR...
2020-06-29 Paul Mackerrascore: Implement CFAR register
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth
2020-06-29 Michael NeulingMerge pull request #214 from shingarov/fix-ld-target
2020-06-26 Boris ShingarovFix ld error in elf maketarget
2020-06-25 Benjamin Herrenschmidttests: Add updated micropython build with 16550 support
2020-06-25 Benjamin Herrenschmidtsim_console: Fix polling to check for POLLIN
2020-06-25 Benjamin Herrenschmidtuart: Make 16550 the default
2020-06-23 Benjamin Herrenschmidtsyscon: Add flag to indicate the timebase frequency
2020-06-23 Benjamin Herrenschmidtconsole: Add support for the 16550 UART
2020-06-23 Benjamin Herrenschmidtuart: Add a simulation model for the 16550 compatible...
2020-06-23 Benjamin Herrenschmidtuart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
2020-06-23 Benjamin Herrenschmidtconsole: Cleanup console API
2020-06-23 Benjamin Herrenschmidtuart: Import and hook up opencore 16550 compatible...
2020-06-23 Benjamin Herrenschmidtex1: Add SPR_TBU support
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller
2020-06-23 Michael NeulingMerge pull request #211 from shenki/spi-constraint
2020-06-23 Joel Stanleyspi: Fix dat_i_l constraints
2020-06-23 Michael NeulingMerge pull request #210 from ozbenh/xics
2020-06-22 Benjamin Herrenschmidtxics: Add support for reduced priority field size
2020-06-19 Benjamin Herrenschmidtxics: Add simple ICS
2020-06-19 Benjamin Herrenschmidtxics/icp: MFRR starts at 0xff not 0x00
2020-06-19 Benjamin Herrenschmidttests/xics: Ensure no compiler optimisations in delay()
2020-06-19 Benjamin Herrenschmidtxics: ICP should be big endian !
2020-06-19 Benjamin Herrenschmidttests: Fix Makefile.test to not allow host includes
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
2020-06-15 Paul Mackerrasexecute1: Reduce width of the result mux to help timing
2020-06-15 Paul Mackerrascore: Implement a simple branch predictor
2020-06-15 Paul Mackerrasdecode1: Improve timing for slow SPR decode path
2020-06-14 Paul Mackerrasdecode1: Add a stash buffer to the output
2020-06-14 Benjamin Herrenschmidtsoc: Slight cleanup of IRQ assignments
2020-06-14 Benjamin Herrenschmidtsoc: Rename uart_dat8 to uart0_dat8
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
2020-06-13 Jonathan BalkindMinor refactor of icache to make less dependent on...
2020-06-13 Paul Mackerrasdcache: Reduce back-to-back store latency from 3 cycles...
2020-06-13 Benjamin Herrenschmidtsoc: Don't require dram wishbones signals to be wired...
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
2020-06-13 Paul Mackerrasmmu: Take an extra cycle to do TLB invalidations
2020-06-13 Paul Mackerrasdcache: Reduce latencies and improve timing
2020-06-13 Paul Mackerrasdecode: Work out ispr1/ispr2 in parallel with decode...
2020-06-13 Paul Mackerrasloadstore1: Reduce busy cycles
2020-06-13 Paul Mackerrasloadstore1: Complete mfspr/mtspr a cycle later
2020-06-13 Paul Mackerrascore: Use a busy signal rather than a stall
2020-06-13 Paul Mackerrasicache: Improve latencies when reloading cache lines
2020-06-13 Paul Mackerrasmultiply: Use DSP48 slices for multiplication on Xilinx...
2020-06-13 Paul Mackerrasmultiply: Move selection of result bits into execute1
2020-06-13 Paul Mackerrascore: Double the dcache and icache sizes
2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
2020-06-13 Paul MackerrasAdd core logging
2020-06-13 Paul Mackerrasscripts/mw_debug: Make progress counts display on one...
2020-06-13 Paul Mackerrastests/xics: Fix assumption that interrupts happen immed...
2020-06-13 Paul Mackerrasregister_file: Report value being written before assert...
2020-06-13 Paul MackerrasMerge pull request #205 from ozbenh/timing
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-13 Benjamin Herrenschmidtsyscon: Remove combinational loop on ack and stall
2020-06-13 Benjamin Herrenschmidtbram: Remove combinational loop on stall
2020-06-13 Benjamin Herrenschmidtuart: Remove combinational loops on ack and stall signal
2020-06-13 Benjamin Herrenschmidtspi: Add booting from flash to litedram init
2020-06-13 Benjamin Herrenschmidtspi: Add simulation support
2020-06-12 Dan Horákflash-arty: update error message (#203)
2020-06-12 Benjamin Herrenschmidtdmi: Add ASYNC_REG attribute on synchronizers (#200)
2020-06-12 Benjamin Herrenschmidticache: Latch PLRU victim output (#199)
2020-06-12 Paul MackerrasMerge pull request #198 from ozbenh/litedram
2020-06-12 Benjamin Herrenschmidtspi: Add SPI Flash controller
2020-06-12 Benjamin Herrenschmidtlitedram: L2 use latched refill_index
2020-06-12 Benjamin Herrenschmidtlitedram: Pipeline store acks in L2
2020-06-12 Benjamin Herrenschmidtarty/nexys-video: Update XDC
2020-06-12 Benjamin Herrenschmidtlitedram: Add stash buffer to the L2 cache wishbone...
2020-06-12 Benjamin Herrenschmidtlitedram: Defer clearing of tags & valids to improve...
2020-06-12 Benjamin Herrenschmidtlitedram: Improve dram_tb error output
2020-06-12 Anton BlanchardMerge pull request #201 from mikey/github-actions
2020-06-11 Michael NeulingMove from travis to github workflow
2020-06-10 Paul MackerrasMerge pull request #194 from ozbenh/misc
2020-06-10 Benjamin Herrenschmidtgitignore: Add more exlusions
2020-06-10 Benjamin Herrenschmidtlitedram: Fix DRAM init mem using too many address...
2020-06-10 Benjamin Herrenschmidtlitedram: Remove remnants of riscv-inits
2020-06-10 Benjamin Herrenschmidtmw_debug: Add "save" function to save memory to a file
2020-06-10 Benjamin Herrenschmidtsw: Properly mask syscon register fields
2020-06-09 Michael NeulingMerge pull request #196 from ozbenh/makefile-lib-fix
2020-06-09 Michael NeulingMerge pull request #195 from shenki/nexys-video
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