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openpower-isa.git
2021-12-18
Luke Kenneth...
whoops error in accessing icache.ibus which is an inter...
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2021-12-17
Mikolaj Wielgus
Call the simulator-generated C using the CFFI
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2021-12-16
Luke Kenneth...
bug where t1 was set to zero but s2 was not in imdct36_...
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2021-12-16
Luke Kenneth...
start/stop wb_get in TestRunnerBase, otherwise it never...
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2021-12-15
Luke Kenneth...
must read off of ibus in wb_get TestRunnerBase
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2021-12-14
Mikolaj Wielgus
Add CFFI as dependency
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2021-12-13
Tobias Platen
add namedtuple MSRSpec
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2021-12-12
Luke Kenneth...
copy over fake OP_FETCH_FAILED and instruction on...
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2021-12-12
Luke Kenneth...
enable mmu_cache_wb for wb_get mode in TestRunnerBase
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2021-12-12
Luke Kenneth...
add pretty-print of MMU memory to be used for a TestRun...
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2021-12-11
Luke Kenneth...
remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
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2021-12-11
Luke Kenneth...
use concat in ternlogi to reduce code size
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2021-12-10
Jacob Lifshay
add ternlogi to SVP64Asm
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2021-12-10
Jacob Lifshay
format code
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2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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2021-12-10
Jacob Lifshay
add .gitignore to ignore the generated vhdl
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2021-12-09
Luke Kenneth...
add I-Cache wishbone bus to wb_get when MMU and ROM...
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2021-12-09
Luke Kenneth...
add warning about creation of "-.csv" which indicates...
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2021-12-09
Luke Kenneth...
add FAST SPRs temporarily to power_enums
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2021-12-09
Jacob Lifshay
make ternlogi tests run
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2021-12-09
Jacob Lifshay
rename ternaryi to ternlogi
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2021-12-09
Jacob Lifshay
add initial ternlogi pseudo-code
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2021-12-08
Luke Kenneth...
add instr_fault to PowerDecoder2
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2021-12-08
Luke Kenneth...
whitespace
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2021-12-08
Luke Kenneth...
code-comments for LDSTException.instr_fault
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2021-12-08
Luke Kenneth...
add an on_Display function which is being used by some...
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2021-12-08
Luke Kenneth...
found a way to print out the names of the signals
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2021-12-08
Luke Kenneth...
absolute import again
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2021-12-08
Luke Kenneth...
use full-path imports (so we know where they come from)
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2021-12-08
Mikolaj Wielgus
WIP: Output C instead of Python for Nmigen simulation
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2021-12-08
Mikolaj Wielgus
Source Nmigen simulator from this repository
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2021-12-07
Luke Kenneth...
whoops wrong number
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2021-12-07
Luke Kenneth...
add OP_FETCH_FAILED micro-op
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2021-12-07
Jacob Lifshay
fix broken url
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2021-12-05
Tobias Platen
fix microwatt_mmu and and wishbone_memory output in...
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2021-12-05
Luke Kenneth...
connect to dcache.bus standard interface when using...
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2021-12-05
Luke Kenneth...
correct import of wb_get function
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2021-12-04
Luke Kenneth...
add name parameter to wb_get
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2021-12-04
Luke Kenneth...
add wb_get function for emulating wishbone interface
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2021-12-04
Luke Kenneth...
raise a MemException in ISACaller RADIXMMU
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2021-12-04
Luke Kenneth...
enable MMU in SimRunner if requested. now HDL and...
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2021-12-04
Luke Kenneth...
test in SimState for access to RADIX memory, bypass...
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2021-12-03
Luke Kenneth...
add a namedtuple LDSTExceptionTuple which allows obtaining
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2021-12-03
Luke Kenneth...
add link to exceptions in gtkw traces
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2021-12-02
Luke Kenneth...
regspec_decode_write now stores the decoded write info...
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2021-12-02
Luke Kenneth...
specify length in RegDecodeInfo explicitly so that...
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2021-12-02
Luke Kenneth...
use namedtuple in get_rdflags
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2021-12-02
Luke Kenneth...
use namedtuple for regspec_decode
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2021-12-02
Luke Kenneth...
add module to regspec_decode_* and get_rdflags
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2021-12-02
Jacob Lifshay
move ternlogi to SHIFT_ROT unit
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2021-12-02
Jacob Lifshay
fix sv_analysis command, cuz script created by setup...
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2021-12-02
Jacob Lifshay
format code
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2021-12-01
Luke Kenneth...
fix expected state in hazard test
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2021-12-01
Luke Kenneth...
fix expected state in hazard case_regression_1
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2021-12-01
Luke Kenneth...
add a proper twin addi regression which tests Reservati...
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2021-12-01
Luke Kenneth...
add regspec_decode which takes readmode arg and returns...
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2021-11-30
Dmitry Selyutin
sv_analysis: decouple declarations and definitions
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2021-11-30
Dmitry Selyutin
sv_analysis: use is instead of eq for enums
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2021-11-30
Dmitry Selyutin
sv_analysis: fix single-line binutils comments
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2021-11-30
Luke Kenneth...
add randomised hazard test
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2021-11-30
Luke Kenneth...
add two more hazard tests
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2021-11-30
Luke Kenneth...
attempting to use PowerDecode2 in non-svp64 mode
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2021-11-27
Dmitry Selyutin
sv_analysis: decouple common disclaimer
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2021-11-27
Dmitry Selyutin
sv_analysis: introduce stub binutils format
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2021-11-27
Dmitry Selyutin
sv_analysis: support format argument
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2021-11-27
Luke Kenneth...
add extra overlap hazard test
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2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb using exts...
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2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb in alu_cases...
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2021-11-26
R Veera Kumar
Shorten expected state code for case_rand in alu_cases...
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2021-11-26
R Veera Kumar
Shorten case_rand_imm alu test case code
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2021-11-26
R Veera Kumar
Make carry_out32 variable boolean and expected state...
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2021-11-25
R Veera Kumar
Shortened code in case_addis_nonzero_r0 alu test case
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2021-11-25
R Veera Kumar
Correct add-equal operator in case_rand_imm
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2021-11-25
R Veera Kumar
Short the code of case_rand_imm
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2021-11-24
R Veera Kumar
Fix line so that 80 characters per line is kept and...
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2021-11-24
R Veera Kumar
Add expected state to case_rand_imm in alu_cases unit...
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2021-11-24
Luke Kenneth...
corrections to hazard overlap test
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2021-11-24
Luke Kenneth...
add extra hazard unit tests
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2021-11-24
Luke Kenneth...
tidyup on case_0_adde
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2021-11-24
Luke Kenneth...
correct write-after-write hazard test (expected values)
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2021-11-23
R Veera Kumar
Add expected state to case_0_adde in alu_cases unit...
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2021-11-23
Luke Kenneth...
add write-after-write hazard test for inorder core
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2021-11-23
R Veera Kumar
Add expected state to case_rand in alu_cases unit test
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2021-11-23
R Veera Kumar
Add expected state to case_addis_nonzero_r0 in alu_case...
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2021-11-23
R Veera Kumar
Add expected state to case_extsb in alu_cases unit...
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2021-11-23
R Veera Kumar
Add computed CR0 to expected version of case_adde_0
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2021-11-22
Luke Kenneth...
add expected version of case_adde_0
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2021-11-22
Luke Kenneth...
adding a couple more hazard avoidance cases
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2021-11-22
R Veera Kumar
Add expected state to case_cmpeqb in alu_cases unit...
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2021-11-22
R Veera Kumar
Add expected state to case_cmplw_microwatt_1 in alu_cas...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpli_microwatt in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0_disasm...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0 in alu_case...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_4 in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_3 in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_1 in alu_cases...
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2021-11-21
Luke Kenneth...
sigh, for overlap mode there is no safe way to get...
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2021-11-21
Luke Kenneth...
move dump state to base class State in test API
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2021-11-21
R Veera Kumar
Add expected state to case_cmp3 in alu_cases unit test
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2021-11-21
R Veera Kumar
Add expected state to case_cmp2 in alu_cases unit test
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