nmigen.git
2019-01-18 whitequarkback.rtlil: only emit each AnyConst/AnySeq cell once.
2019-01-17 Alain Péteutcli: add missing default for `generate`
2019-01-17 whitequarklib.fifo: add basic formal specification.
2019-01-17 whitequarkhdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 whitequarkhdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 whitequarkformal: extract from toplevel module.
2019-01-17 whitequarkhdl.xfrm: add SampleLowerer.
2019-01-17 whitequarkhdl.ast: add Sample.
2019-01-16 whitequarklib.fifo: port sync FIFO queues from Migen.
2019-01-16 whitequarkhdl.ast: fix naming of Signal.like() signals when trace...
2019-01-16 whitequarkback.rtlil: slightly nicer naming for $next signals...
2019-01-16 whitequarkback.rtlil: rename \sig$next to $next$sig.
2019-01-16 whitequarkTravis: install SymbiYosys and Yices2.
2019-01-15 whitequarkUnbreak 655d02d5.
2019-01-15 William D.... back.rtlil: Generate $anyconst and $anyseq cells.
2019-01-15 William D.... hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method...
2019-01-15 William D.... hdl.ast: Add AnyConst and AnySeq value types.
2019-01-15 Sebastien BourdeauducqREADME: add LambdaConcept sponsorship
2019-01-14 whitequarklib.io: pass pin to platform.get_tristate().
2019-01-14 whitequarkhdl.ir: allow explicitly requesting flattening.
2019-01-14 whitequarklib.io: lower to platform-independent tristate buffer.
2019-01-14 whitequarkhdl: make ClockSignal and ResetSignal usable on LHS.
2019-01-13 whitequarkhdl.dsl: cases wider than switch test value are unreach...
2019-01-13 whitequarkhdl.dsl: accept (but warn on) cases wider than switch...
2019-01-13 whitequarkback.pysim: handle non-driven, non-port signals.
2019-01-13 whitequarkback.verilog: better error message if Yosys is not...
2019-01-08 whitequarkback.verilog: remove undriven check.
2019-01-06 Adam GreigGive the top level scope a name to fix VCD hierarchy.
2019-01-02 whitequarkhdl.ast: allow slicing [n:n] into n-bit value.
2019-01-02 whitequarkback.rtlil: translate empty slices correctly.
2019-01-02 William D.... back.rtlil: Generate RTLIL for Assert/Assume statements.
2019-01-02 William D.... hdl.xfrm: Add Assert and Assume abstract methods for...
2019-01-02 William D.... hdl.dsl: Support Assert and Assume where an Assign...
2019-01-02 William D.... hdl.ast: Add Assert and Assign statements.
2019-01-01 whitequarkhdl.ast: experimentally add Value._as_const.
2019-01-01 whitequarkback.rtlil: fix typo.
2019-01-01 whitequarkhdl.rec: include record name in error message.
2019-01-01 whitequarkhdl.rec: use a helpful error on unknown field reference.
2019-01-01 whitequarkhdl.mem: add DummyPort, for testing and verification.
2018-12-31 whitequarkback.rtlil: match shape of Array elements to ArrayProxy...
2018-12-31 whitequarkback.rtlil: fix typo.
2018-12-29 whitequarklib.cdc: fix tests to actually run.
2018-12-29 whitequarkback.pysim: warn if simulation is not run.
2018-12-28 whitequarkhdl.rec: add basic record support.
2018-12-28 whitequarktracer: factor out get_src_loc().
2018-12-27 whitequarklib.coding: fix tests to actually run, and fix code...
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing().
2018-12-27 whitequarkhdl.mem: add missing __all__.
2018-12-26 Jean-François... compat.genlib.coding: fix import.
2018-12-26 whitequarklib.coding: port from Migen.
2018-12-26 whitequarklib.cdc: add tests for MultiReg.
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of...
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs.
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values...
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver).
2018-12-26 whitequarkhdl.dsl: add signal decoder to FSM state signal.
2018-12-26 whitequarkhdl.dsl: implement FSM.
2018-12-26 whitequarkback.rtlil: clarify $verilog_initial_trigger behavior...
2018-12-24 whitequarkback.rtlil: unbreak d47c1f8a.
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic.
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word.
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty...
2018-12-24 whitequarkback.rtlil: always output negative values as two's...
2018-12-23 whitequarkback.rtlil: emit dummy logic to work around Verilog...
2018-12-23 whitequarkback.rtlil: do not translate empty fragments.
2018-12-23 whitequarkback.rtlil: only translate switch tests once.
2018-12-23 whitequarkcli: generate: guess file type from extension.
2018-12-23 whitequarkback.rtlil: fix swapped operands in mux codegen.
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation.
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA...
2018-12-22 whitequarkcompat.genlib.fsm: fix naming for non-Signal LHS.
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses...
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC.
2018-12-22 whitequarkback.rtlil: split processes as finely as possible.
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC.
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer.
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 whitequarkback.rtlil: always initialize the entire memory.
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce...
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory.
2018-12-22 whitequarkback.verilog: do not rename internal signals.
2018-12-22 whitequarkcompat: fix confusing naming for memory port address...
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the...
2018-12-22 whitequarkcompat: do not finalize native submodules twice.
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports.
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings.
2018-12-21 whitequarkcompat: provide verilog.convert shim.
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from...
2018-12-21 whitequarkcompat: provide Memory shim.
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct...
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments...
2018-12-21 whitequarkhdl.mem: use different naming for array signals.
2018-12-21 whitequarkhdl.mem: add simulation model for memory.
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots.
2018-12-21 whitequarkhdl.mem: add tests for all error conditions.
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa...
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment...
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports.
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