2019-04-08 |
Eddie Hung | $_XILINX_SHREG_ to preserve src attribute |
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2019-04-08 |
Eddie Hung | Update CHANGELOG |
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2019-04-08 |
Eddie Hung | Merge branch 'undo_pr895' into xc7srl |
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2019-04-08 |
Eddie Hung | Undo #895 by instead setting an attribute |
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2019-04-08 |
Eddie Hung | Cope with undoing #895 |
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2019-04-08 |
Eddie Hung | Revert "Remove handling for $pmux, since #895" |
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2019-04-06 |
Eddie Hung | Call shregmap twice -- once for variable, another for... |
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2019-04-05 |
Eddie Hung | Merge branch 'eddie/fix_retime' into xc7srl |
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2019-04-05 |
Eddie Hung | Add retime test |
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2019-04-05 |
Eddie Hung | Fix S0 -> S1 |
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2019-04-05 |
Eddie Hung | Move dffinit til after abc |
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2019-04-05 |
Eddie Hung | Merge branch 'eddie/fix_retime' into xc7srl |
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2019-04-05 |
Eddie Hung | Move techamp t:$_DFF_?N? to before abc call |
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2019-04-05 |
Eddie Hung | Retry |
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2019-04-05 |
Eddie Hung | "&nf -D 0" fails => use "-D 1" instead |
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2019-04-05 |
Eddie Hung | Resolve @daveshah1 comment, update synth_xilinx help |
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2019-04-05 |
Eddie Hung | synth_xilinx to techmap FFs after abc call, otherwise... |
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2019-04-05 |
Eddie Hung | abc -dff now implies "-D 0" otherwise retiming doesn... |
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2019-04-05 |
Eddie Hung | techmap inside map_cells stage |
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2019-04-05 |
Clifford Wolf | Add "read_ilang -lib" |
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2019-04-04 |
Clifford Wolf | Added missing argument checking to "mutate" command |
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2019-04-04 |
Eddie Hung | Merge branch 'map_cells_before_map_luts' into xc7srl |
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2019-04-04 |
Eddie Hung | Missing techmap entry in help |
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2019-04-04 |
Eddie Hung | Use soft-logic, not LUT3 instantiation |
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2019-04-04 |
Eddie Hung | Merge branch 'map_cells_before_map_luts' into xc7srl |
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2019-04-04 |
Eddie Hung | synth_xilinx to map_cells before map_luts |
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2019-04-04 |
Eddie Hung | Cleanup comments |
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2019-04-04 |
Eddie Hung | t:$dff* -> t:$dff t:$dffe |
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2019-04-03 |
Eddie Hung | Remove handling for $pmux, since #895 |
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2019-04-03 |
Eddie Hung | -nosrl meant when -nobram |
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2019-04-03 |
Eddie Hung | Remove duplicate STARTUPE2 |
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2019-04-03 |
Eddie Hung | Disable shregmap in synth_xilinx if -retime |
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2019-04-03 |
Eddie Hung | Add changelog entry |
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2019-04-03 |
Eddie Hung | Merge pull request #913 from smunaut/fix_proc_mux |
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2019-04-03 |
Sylvain Munaut | proc_mux: Fix crash when trying to optimize non-existan... |
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2019-04-03 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7srl |
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2019-04-03 |
Clifford Wolf | Merge pull request #912 from YosysHQ/bram_addr_en |
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2019-04-03 |
Clifford Wolf | Merge pull request #910 from ucb-bar/memupdates |
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2019-04-02 |
David Shah | memory_bram: Consider read enable for address expansion... |
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2019-04-02 |
Eddie Hung | Merge pull request #895 from YosysHQ/pmux2shiftx |
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2019-04-01 |
Jim Lawson | Refine memory support to deal with general Verilog... |
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2019-03-29 |
Clifford Wolf | Merge pull request #907 from YosysHQ/clifford/fix906 |
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2019-03-29 |
Clifford Wolf | Build Verilog parser with -DYYMAXDEPTH=100000, fixes... |
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2019-03-28 |
Clifford Wolf | Merge pull request #901 from trcwm/libertyfixes |
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2019-03-28 |
Clifford Wolf | Merge pull request #903 from YosysHQ/bram_reset_transp |
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2019-03-27 |
David Shah | memory_bram: Reset make_transp when growing read ports |
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2019-03-27 |
Niels Moseley | Liberty file parser now accepts superfluous ; |
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2019-03-27 |
Niels Moseley | Liberty file parser now accepts superfluous ; |
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2019-03-27 |
Niels Moseley | Liberty file parser now accepts superfluous ; |
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2019-03-27 |
Clifford Wolf | Add "read -verific" and "read -noverific" |
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2019-03-27 |
Clifford Wolf | Add "rename -output" |
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2019-03-27 |
Clifford Wolf | Improve "rename" help message |
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2019-03-26 |
Clifford Wolf | Add "cutpoint -undef" |
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2019-03-26 |
Clifford Wolf | Add "hdlname" attribute |
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2019-03-26 |
Clifford Wolf | Fix "verific -extnets" for more complex situations |
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2019-03-25 |
Eddie Hung | synth_xilinx to use shregmap with -minlen 3 |
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2019-03-25 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7srl |
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2019-03-25 |
Clifford Wolf | Add "cutpoint" pass |
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2019-03-25 |
Eddie Hung | Create one $shiftx per bit in width |
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2019-03-25 |
Clifford Wolf | Merge pull request #896 from YosysHQ/transp_fixes |
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2019-03-25 |
Clifford Wolf | Merge pull request #897 from trcwm/libertyfixes |
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2019-03-25 |
Niels Moseley | spaces -> tabs |
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2019-03-25 |
Niels Moseley | EOL is now accepted as ';' replacement on lines that... |
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2019-03-24 |
Niels Moseley | Updated the liberty parser to accept [A:B] ranges ... |
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2019-03-24 |
David Shah | memory_bram: Fix multiclock make_transp |
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2019-03-23 |
Eddie Hung | Add a pmux-to-shiftx optimisation to proc_mux |
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2019-03-23 |
Eddie Hung | Cope with SHREG not having E port; Revert $pmux fine... |
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2019-03-23 |
Clifford Wolf | Add "mutate -none -mode", "mutate -mode none" |
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2019-03-23 |
Clifford Wolf | Add "mutate -s <filename>" |
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2019-03-23 |
Clifford Wolf | Merge pull request #893 from YosysHQ/clifford/btormeminit |
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2019-03-23 |
Clifford Wolf | Add support for memory initialization to write_btor |
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2019-03-23 |
Clifford Wolf | Fix BTOR output tags syntax in writye_btor |
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2019-03-23 |
Clifford Wolf | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend... |
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2019-03-23 |
Eddie Hung | Add support for SHREGMAP+$mux, also fine tune $pmux |
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2019-03-23 |
Eddie Hung | Leftover printf |
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2019-03-23 |
Eddie Hung | Fixes for multibit |
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2019-03-23 |
Eddie Hung | Working for 1 bit |
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2019-03-22 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7srl |
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2019-03-22 |
Clifford Wolf | Merge pull request #889 from YosysHQ/clifford/fix888 |
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2019-03-22 |
Clifford Wolf | Merge pull request #890 from YosysHQ/clifford/fix887 |
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2019-03-22 |
David Shah | Merge pull request #891 from YosysHQ/xilinx_keep |
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2019-03-22 |
David Shah | xilinx: Add keep attribute where appropriate |
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2019-03-22 |
Clifford Wolf | Trim init attributes when resizing FFs in "wreduce... |
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2019-03-21 |
Eddie Hung | Add '-nosrl' option to synth_xilinx |
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2019-03-21 |
Clifford Wolf | Fix mem2reg handling of memories with upto data ports... |
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2019-03-21 |
Clifford Wolf | Improve "read_verilog -dump_vlog[12]" handling of upto... |
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2019-03-21 |
Clifford Wolf | Improve read_verilog debug output capabilities |
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2019-03-21 |
Eddie Hung | Opt |
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2019-03-20 |
Eddie Hung | Fix spacing |
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2019-03-20 |
Eddie Hung | Fine tune cells_map.v |
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2019-03-20 |
Eddie Hung | Revert $__SHREG_ to orig; use $__XILINX_SHREG for varia... |
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2019-03-20 |
Eddie Hung | Add support for variable length Xilinx SRL > 128 |
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2019-03-19 |
Eddie Hung | Restore original synth_xilinx commands |
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2019-03-19 |
Eddie Hung | Fix spacing |
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2019-03-19 |
Eddie Hung | shregmap -tech xilinx to delete $shiftx for var length SRL |
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2019-03-19 |
Eddie Hung | Fix INIT for variable length SRs that have been bumped... |
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2019-03-19 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7srl |
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2019-03-19 |
Eddie Hung | Make output port a non chain user |
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2019-03-19 |
Clifford Wolf | Merge pull request #885 from YosysHQ/clifford/fix873 |
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2019-03-19 |
Clifford Wolf | Add Xilinx negedge FFs to synth_xilinx dffinit call... |
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next |