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yosys.git
2022-05-30
Daniel Huisman
Fix typo in emcc flags (typo introduced by #3053)
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2022-05-30
Jannis Harder
verilog: fix size and signedness of array querying...
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2022-05-28
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2022-05-27
Patrick Urban
gatemate: Fix minor issues with `memory_libmap` (#3343)
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2022-05-27
Miodrag Milanović
Merge pull request #3333 from mohamed/feature/tmpdir
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2022-05-27
Miodrag Milanovic
Cleanup, and fix windows
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2022-05-27
Mohamed A....
Observe $TMPDIR variable when creating tmp files
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2022-05-27
Miodrag Milanović
Merge pull request #3341 from mmicko/unused_vars
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2022-05-27
Miodrag Milanovic
Upload emscripten artifact
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2022-05-27
Miodrag Milanovic
Remove set but unused variable
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2022-05-27
Miodrag Milanovic
Add emcc build (stuck if all cpus used on GH)
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2022-05-27
Miodrag Milanovic
Proper std::move
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2022-05-27
Miodrag Milanovic
Use proper operator
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2022-05-27
Miodrag Milanović
Merge pull request #3053 from DanielHuisman/pr-2
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2022-05-26
github-actions...
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2022-05-25
Jannis Harder
verilog: fix $past's signedness
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2022-05-25
Miodrag Milanović
Merge pull request #3011 from DanielHuisman/pr-1
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2022-05-25
Jannis Harder
Merge pull request #3335 from programmerjake/divfloor...
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2022-05-25
Miodrag Milanović
Merge pull request #3138 from DanielG/fix-git-rev
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2022-05-25
Daniel Gröber
Make GIT_REV logic work in release tarballs
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2022-05-25
Jannis Harder
verilog: fix signedness when removing unreachable cases
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2022-05-24
Jacob Lifshay
add $divfloor support to write_smt2
divfloor-in-write_smt2
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2022-05-24
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2022-05-23
Miodrag Milanović
Merge pull request #3332 from YosysHQ/verific_f
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2022-05-23
Miodrag Milanovic
fix text to fit 80 columns
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2022-05-23
Miodrag Milanovic
Update verific command file documentation
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2022-05-23
Miodrag Milanovic
Use analysis mode if set in file
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2022-05-23
Miodrag Milanović
Merge pull request #3331 from YosysHQ/git_rev_fix
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2022-05-23
Jannis Harder
Change way to get commit sha
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2022-05-23
gatecat
abc9_ops: Don't leave unused derived modules lying...
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2022-05-21
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2022-05-20
Jannis Harder
Merge pull request #3324 from jix/confusing-select...
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2022-05-19
Jannis Harder
select: Fix -assert-none and -assert-any error output...
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2022-05-19
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2022-05-18
Marcelina Kościelnicka
Add memory_bmux2rom pass.
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2022-05-18
Marcelina Kościelnicka
Add memory_libmap tests.
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2022-05-18
Marcelina Kościelnicka
gatemate: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
machxo2: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
efinix: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
anlogic: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
ice40: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
xilinx: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
gowin: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
nexus: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
ecp5: Use `memory_libmap` pass.
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2022-05-18
Marcelina Kościelnicka
Add memory_libmap pass.
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2022-05-18
Marcelina Kościelnicka
proc_rom: Add special handling of const-0 address bits.
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2022-05-18
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2022-05-17
Miodrag Milanović
Merge pull request #3310 from robinsonb5-PRs/master
master
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2022-05-17
Marcelina Kościelnicka
opt_ffinv: Use ModIndex instead of ModWalker.
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2022-05-16
Alastair M...
Use log_warning when Tcl_Init fails, report error with...
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2022-05-16
Jannis Harder
Merge pull request #3314 from jix/sva_value_change_logi...
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2022-05-14
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2022-05-13
Marcelina Kościelnicka
Add opt_ffinv pass.
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2022-05-13
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2022-05-12
Marcelina Kościelnicka
Add proc_rom pass.
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2022-05-11
Jannis Harder
verific: Use new value change logic also for $stable...
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2022-05-10
Alastair M...
Now calls Tcl_Init after creating the interp, fixes...
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2022-05-10
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2022-05-09
Jannis Harder
Merge pull request #3305 from jix/sva_value_change_logic
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2022-05-09
Jannis Harder
Merge pull request #3297 from jix/sva_nested_clk_else
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2022-05-09
Jannis Harder
verific: Improve logic generated for SVA value change...
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2022-05-09
Miodrag Milanovic
Next dev cycle
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2022-05-09
Miodrag Milanovic
Release version 0.17
yosys-0.17
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2022-05-09
Miodrag Milanovic
Update CHANGELOG
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2022-05-09
Miodrag Milanovic
Update manual
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2022-05-09
Miodrag Milanović
Merge pull request #3299 from YosysHQ/mmicko/sim_memory
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2022-05-09
Miodrag Milanovic
Fix running sva tests
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2022-05-08
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2022-05-07
Marcelina Kościelnicka
opt_mem: Remove constant-value bit lanes.
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2022-05-07
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2022-05-06
Miodrag Milanovic
include latest abc changes
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2022-05-06
Miodrag Milanovic
include latest abc changes
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2022-05-06
Miodrag Milanović
Merge pull request #3300 from imhcyx/master
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2022-05-06
Miodrag Milanovic
Include abc change to fix FreeBSD build
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2022-05-06
Miodrag Milanovic
Handle possible non-memory indexed data
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2022-05-05
imhcyx
memory_share: fix wrong argidx in extra_args
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2022-05-05
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2022-05-04
Marcelina Kościelnicka
abc: Use dict/pool instead of std::map/std::set
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2022-05-04
Miodrag Milanovic
map memory location to wire value, if memory is convert...
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2022-05-04
Miodrag Milanovic
fix crash when no fst input
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2022-05-04
Miodrag Milanovic
Start restoring memory state from VCD/FST
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2022-05-04
Claire Xenia...
Add propagated clock signals into btor info file
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2022-05-03
Jannis Harder
verific: Fix conditions of SVAs with explicit clocks...
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2022-05-03
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2022-05-02
Miodrag Milanovic
AIM file could have gaps in or between inputs and inits
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2022-04-30
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2022-04-29
Miodrag Milanović
Merge pull request #3294 from YosysHQ/micko/verific_mer...
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2022-04-29
Miodrag Milanovic
Ignore merging past ffs that we are not properly merging
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2022-04-26
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2022-04-25
Rick Luiken
Add missing parameters for ecp5
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2022-04-25
Jannis Harder
Merge pull request #3287 from jix/smt2-conditional...
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2022-04-25
Jannis Harder
Merge pull request #3257 from jix/tribuf-formal
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2022-04-25
Miodrag Milanović
Merge pull request #3290 from mpasternacki/bugfix/freeb...
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2022-04-25
Miodrag Milanović
Merge pull request #3289 from YosysHQ/micko/sim_improve
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2022-04-24
Maciej Pasternacki
Fix build on FreeBSD, which has no alloca.h
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2022-04-22
Miodrag Milanovic
Match $anyseq input if connected to public wire
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2022-04-22
Miodrag Milanovic
Treat $anyseq as input from FST
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2022-04-22
Miodrag Milanovic
Ignore change on last edge
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2022-04-22
Miodrag Milanovic
Last sample from input does not represent change
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