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litex.git
2013-03-12
Sebastien Bourdeauducq
sim/generic: support implicit get_fragment
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2013-03-12
Sebastien Bourdeauducq
vpi: make it work by default on Arch
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2013-03-12
Sebastien Bourdeauducq
examples/basic: use new APIs
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2013-03-12
Sebastien Bourdeauducq
fhdl/verilog: implicit get_fragment
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2013-03-12
Sebastien Bourdeauducq
fhdl/specials/Memory: automatic name#
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2013-03-12
Sebastien Bourdeauducq
bank: automatic register naming
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2013-03-12
Sebastien Bourdeauducq
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
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2013-03-12
Sebastien Bourdeauducq
fhdl/tracer: recognize LOAD_DEREF opcode
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2013-03-11
Sebastien Bourdeauducq
fhdl/tracer: remove leading underscores from names
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2013-03-11
Sebastien Bourdeauducq
README: update
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2013-03-11
Sebastien Bourdeauducq
bus/asmibus: use implicit finalization
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2013-03-10
Sebastien Bourdeauducq
Fix Register name conflict between Pytholite and Bank
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2013-03-10
Sebastien Bourdeauducq
bank/eventmanager: use module and autoreg
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2013-03-10
Sebastien Bourdeauducq
bus/asmibus: use fhdl.module API
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2013-03-10
Sebastien Bourdeauducq
fhdl/module: replace autofragment
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2013-03-10
Sebastien Bourdeauducq
bank/description/AutoReg: check that get_memories and...
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2013-03-09
Sebastien Bourdeauducq
bank/csrgen: BankArray
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2013-03-09
Sebastien Bourdeauducq
bank/description: AutoReg
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2013-03-09
Sebastien Bourdeauducq
migen/fhdl/autofragment: factorize
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: remove legacy functions
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2013-03-09
Sebastien Bourdeauducq
fhdl/tools/flat_iteration: generalize
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: fix submodules
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: empty build_fragment by default
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2013-03-09
Sebastien Bourdeauducq
Use common definition for FinalizeError
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2013-03-08
Sebastien Bourdeauducq
csr/SRAM: support for writes with memory widths larger...
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2013-03-06
Sebastien Bourdeauducq
fhdl/verilog: tristate outputs are always wire
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2013-03-03
Sebastien Bourdeauducq
bus/csr: support memories with larger word width than...
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2013-03-03
Sebastien Bourdeauducq
fhdl/autofragment: bugfixes + add auto_attr
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2013-03-02
Sebastien Bourdeauducq
fhdl/autofragment: FModule
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2013-03-01
Sebastien Bourdeauducq
csr/SRAM: prefix page register with memory name
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2013-02-27
Sebastien Bourdeauducq
fhdl/verilog: insert reset before listing signals
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2013-02-25
Sebastien Bourdeauducq
bank/description: memprefix
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2013-02-25
Sebastien Bourdeauducq
fhdl/specials: allow setting memory name
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2013-02-25
Sebastien Bourdeauducq
uio/ioo: fix specials
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2013-02-24
Sebastien Bourdeauducq
fhdl/specials/Instance: _printintbool -> verilog_printexpr
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2013-02-23
Sebastien Bourdeauducq
examples/psync: cleanup
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2013-02-23
Sebastien Bourdeauducq
examples/basic/psync: demonstrate the new features
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2013-02-23
Sebastien Bourdeauducq
genlib: clock domain crossing elements
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2013-02-23
Sebastien Bourdeauducq
fhdl/verilog: support special lowering and overrides
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2013-02-22
Sebastien Bourdeauducq
examples/fir: better filter
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2013-02-22
Sebastien Bourdeauducq
corelogic -> genlib
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2013-02-22
Sebastien Bourdeauducq
fhdl: inline synthesis directive support
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2013-02-22
Sebastien Bourdeauducq
doc: new 'specials' API
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2013-02-22
Sebastien Bourdeauducq
New 'specials' API
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2013-02-19
Sebastien Bourdeauducq
doc: tristates
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2013-02-19
Sebastien Bourdeauducq
fhdl: TSTriple
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2013-02-14
Sebastien Bourdeauducq
fhdl: tristate support
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2013-02-11
Sebastien Bourdeauducq
fhdl/autofragment: from_attributes
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2013-02-10
Sebastien Bourdeauducq
doc: fix signal desc layout
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2013-02-10
Sebastien Bourdeauducq
Merge branch 'master' of github.com:milkymist/migen
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2013-02-10
Sebastien Bourdeauducq
doc/dataflow: remove ActorNode
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2013-02-10
Sebastien Bourdeauducq
doc/dataflow: remove ALA
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2013-02-10
Sebastien Bourdeauducq
doc: multiple clock domains
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2013-02-10
Sebastien Bourdeauducq
doc: do not inline examples as this never works with...
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2013-02-10
Sebastien Bourdeauducq
doc: update to new Migen APIs
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2013-02-09
Sebastien Bourdeauducq
sim: default runner to Icarus Verilog
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2013-02-09
Sebastien Bourdeauducq
flow/perftools: finish removing ActorNode
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2013-01-24
Sebastien Bourdeauducq
fhdl/structure: store clock domain name
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2013-01-23
Sebastien Bourdeauducq
fhdl/verilog: fix spurious clock/reset signals on multi...
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2013-01-05
Sebastien Bourdeauducq
corelogic: complex arithmetic support
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2013-01-05
Sebastien Bourdeauducq
fhdl: support nested statement lists
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2012-12-19
Sebastien Bourdeauducq
pytholite: fix bug with constant assignment to register
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2012-12-19
Sebastien Bourdeauducq
pytholite: prune unused registers
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2012-12-18
Sebastien Bourdeauducq
Do not use super()
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2012-12-16
Sebastien Bourdeauducq
examples/pytholite: fix imports
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2012-12-14
Sebastien Bourdeauducq
fhdl/tools: bitreverse
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2012-12-14
Sebastien Bourdeauducq
actorlib/sim/SimActor: do not drive busy low when gener...
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2012-12-14
Sebastien Bourdeauducq
Token: support idle_wait
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2012-12-14
Sebastien Bourdeauducq
Move Token to migen.flow.transactions
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2012-12-12
Sebastien Bourdeauducq
replace some forgotten is_abstract()
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2012-12-12
Sebastien Bourdeauducq
Remove ActorNode
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2012-12-06
Sebastien Bourdeauducq
Merge branch 'master' of github.com:milkymist/migen
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2012-12-06
Sebastien Bourdeauducq
fhdl/structure: do not create Signal in Instance when...
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2012-12-06
Sebastien Bourdeauducq
elsewhere: do not create interface in default param
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2012-12-06
Sebastien Bourdeauducq
migen/bank: do not create interface in default param
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2012-12-06
Sebastien Bourdeauducq
bus/csr: add SRAM
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2012-12-06
Sebastien Bourdeauducq
bank/csrgen: interface -> bus
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2012-12-05
Sebastien Bourdeauducq
bank/description: define reset value of read signal
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2012-12-05
Sebastien Bourdeauducq
actorlib/sim: drive busy high until generator is finished
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2012-12-01
Sebastien Bourdeauducq
bus/wishbone/sram: accept memories < 32 bits
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2012-12-01
Sebastien Bourdeauducq
bus/wishbone: add SRAM
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2012-11-30
Sebastien Bourdeauducq
pytholite: fix bit width of selection signal
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2012-11-30
Sebastien Bourdeauducq
pytholite: support signed registers
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2012-11-29
Sebastien Bourdeauducq
corelogic/roundrobin: fix request width (again)
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2012-11-29
Sebastien Bourdeauducq
corelogic/roundrobin: fix request width
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2012-11-29
Sebastien Bourdeauducq
Fix various errors from new bitwidth/signedness system...
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2012-11-29
Sebastien Bourdeauducq
fhdl/verilog: make signal behave as integers in arithme...
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2012-11-29
Sebastien Bourdeauducq
fhdl/structure: add unary minus
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2012-11-29
Sebastien Bourdeauducq
Replace Signal(bits_for(... with Signal(max=...
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2012-11-29
Sebastien Bourdeauducq
New specification for width and signedness
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2012-11-29
Sebastien Bourdeauducq
Refactor Case
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2012-11-28
Sebastien Bourdeauducq
pytholite/reg: use source id in dictionary
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2012-11-28
Sebastien Bourdeauducq
Remove Constant
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2012-11-28
Sebastien Bourdeauducq
examples/sim/dataflow: update to new APIs
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2012-11-28
Sebastien Bourdeauducq
examples/dataflow/dma: update to new APIs
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2012-11-28
Sebastien Bourdeauducq
examples/basic: remove unroll example
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2012-11-28
Sebastien Bourdeauducq
fhdl/structure: improved bits_for function
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2012-11-28
Sebastien Bourdeauducq
visit/NodeTransformer: copy most nodes
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2012-11-28
Sebastien Bourdeauducq
fhdl/tools: use NodeTransformer to lower arrays
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2012-11-26
Sebastien Bourdeauducq
examples/basic/arrays: add array assignment to fragment
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