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nmigen.git
2019-01-19 whitequarklib.fifo: use model equivalence to simplify formal... commit | commitdiff | tree
2019-01-19 whitequarkhdl.ast: implement shape for modulo operator. commit | commitdiff | tree
2019-01-19 whitequarkhdl.ast: add Value.implies. commit | commitdiff | tree
2019-01-19 whitequarkhdl.xfrm: mark internal registers used in lowering... commit | commitdiff | tree
2019-01-19 whitequarkdoc: update COMPAT_SUMMARY. commit | commitdiff | tree
2019-01-19 whitequarkfhdl.specials: add compatibility shim for Tristate. commit | commitdiff | tree
2019-01-19 whitequarklib.fifo: fix simulation read/write methods to take... commit | commitdiff | tree
2019-01-19 whitequarkcompat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOB... commit | commitdiff | tree
2019-01-19 whitequarklib.fifo: formally verify FIFO contract. commit | commitdiff | tree
2019-01-19 whitequarkhdl.ast: give Assert and Assume their own src_loc. commit | commitdiff | tree
2019-01-18 whitequarkback.rtlil: only emit each AnyConst/AnySeq cell once. commit | commitdiff | tree
2019-01-17 Alain Péteutcli: add missing default for `generate` commit | commitdiff | tree
2019-01-17 whitequarklib.fifo: add basic formal specification. commit | commitdiff | tree
2019-01-17 whitequarkhdl.ast: allow sampling ClockSignal, ResetSignal. commit | commitdiff | tree
2019-01-17 whitequarkhdl.ast: add Past, Stable, Rose, Fell. commit | commitdiff | tree
2019-01-17 whitequarkformal: extract from toplevel module. commit | commitdiff | tree
2019-01-17 whitequarkhdl.xfrm: add SampleLowerer. commit | commitdiff | tree
2019-01-17 whitequarkhdl.ast: add Sample. commit | commitdiff | tree
2019-01-16 whitequarklib.fifo: port sync FIFO queues from Migen. commit | commitdiff | tree
2019-01-16 whitequarkhdl.ast: fix naming of Signal.like() signals when trace... commit | commitdiff | tree
2019-01-16 whitequarkback.rtlil: slightly nicer naming for $next signals... commit | commitdiff | tree
2019-01-16 whitequarkback.rtlil: rename \sig$next to $next$sig. commit | commitdiff | tree
2019-01-16 whitequarkTravis: install SymbiYosys and Yices2. commit | commitdiff | tree
2019-01-15 whitequarkUnbreak 655d02d5. commit | commitdiff | tree
2019-01-15 William D.... back.rtlil: Generate $anyconst and $anyseq cells. commit | commitdiff | tree
2019-01-15 William D.... hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... commit | commitdiff | tree
2019-01-15 William D.... hdl.ast: Add AnyConst and AnySeq value types. commit | commitdiff | tree
2019-01-15 Sebastien BourdeauducqREADME: add LambdaConcept sponsorship commit | commitdiff | tree
2019-01-14 whitequarklib.io: pass pin to platform.get_tristate(). commit | commitdiff | tree
2019-01-14 whitequarkhdl.ir: allow explicitly requesting flattening. commit | commitdiff | tree
2019-01-14 whitequarklib.io: lower to platform-independent tristate buffer. commit | commitdiff | tree
2019-01-14 whitequarkhdl: make ClockSignal and ResetSignal usable on LHS. commit | commitdiff | tree
2019-01-13 whitequarkhdl.dsl: cases wider than switch test value are unreach... commit | commitdiff | tree
2019-01-13 whitequarkhdl.dsl: accept (but warn on) cases wider than switch... commit | commitdiff | tree
2019-01-13 whitequarkback.pysim: handle non-driven, non-port signals. commit | commitdiff | tree
2019-01-13 whitequarkback.verilog: better error message if Yosys is not... commit | commitdiff | tree
2019-01-08 whitequarkback.verilog: remove undriven check. commit | commitdiff | tree
2019-01-06 Adam GreigGive the top level scope a name to fix VCD hierarchy. commit | commitdiff | tree
2019-01-02 whitequarkhdl.ast: allow slicing [n:n] into n-bit value. commit | commitdiff | tree
2019-01-02 whitequarkback.rtlil: translate empty slices correctly. commit | commitdiff | tree
2019-01-02 William D.... back.rtlil: Generate RTLIL for Assert/Assume statements. commit | commitdiff | tree
2019-01-02 William D.... hdl.xfrm: Add Assert and Assume abstract methods for... commit | commitdiff | tree
2019-01-02 William D.... hdl.dsl: Support Assert and Assume where an Assign... commit | commitdiff | tree
2019-01-02 William D.... hdl.ast: Add Assert and Assign statements. commit | commitdiff | tree
2019-01-01 whitequarkhdl.ast: experimentally add Value._as_const. commit | commitdiff | tree
2019-01-01 whitequarkback.rtlil: fix typo. commit | commitdiff | tree
2019-01-01 whitequarkhdl.rec: include record name in error message. commit | commitdiff | tree
2019-01-01 whitequarkhdl.rec: use a helpful error on unknown field reference. commit | commitdiff | tree
2019-01-01 whitequarkhdl.mem: add DummyPort, for testing and verification. commit | commitdiff | tree
2018-12-31 whitequarkback.rtlil: match shape of Array elements to ArrayProxy... commit | commitdiff | tree
2018-12-31 whitequarkback.rtlil: fix typo. commit | commitdiff | tree
2018-12-29 whitequarklib.cdc: fix tests to actually run. commit | commitdiff | tree
2018-12-29 whitequarkback.pysim: warn if simulation is not run. commit | commitdiff | tree
2018-12-28 whitequarkhdl.rec: add basic record support. commit | commitdiff | tree
2018-12-28 whitequarktracer: factor out get_src_loc(). commit | commitdiff | tree
2018-12-27 whitequarklib.coding: fix tests to actually run, and fix code... commit | commitdiff | tree
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing(). commit | commitdiff | tree
2018-12-27 whitequarkhdl.mem: add missing __all__. commit | commitdiff | tree
2018-12-26 Jean-François... compat.genlib.coding: fix import. commit | commitdiff | tree
2018-12-26 whitequarklib.coding: port from Migen. commit | commitdiff | tree
2018-12-26 whitequarklib.cdc: add tests for MultiReg. commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of... commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs. commit | commitdiff | tree
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values... commit | commitdiff | tree
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver). commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: add signal decoder to FSM state signal. commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: implement FSM. commit | commitdiff | tree
2018-12-26 whitequarkback.rtlil: clarify $verilog_initial_trigger behavior... commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: unbreak d47c1f8a. commit | commitdiff | tree
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic. commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty... commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: always output negative values as two's... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: emit dummy logic to work around Verilog... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: do not translate empty fragments. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: only translate switch tests once. commit | commitdiff | tree
2018-12-23 whitequarkcli: generate: guess file type from extension. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: fix swapped operands in mux codegen. commit | commitdiff | tree
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA... commit | commitdiff | tree
2018-12-22 whitequarkcompat.genlib.fsm: fix naming for non-Signal LHS. commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: split processes as finely as possible. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: always initialize the entire memory. commit | commitdiff | tree
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce... commit | commitdiff | tree
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory. commit | commitdiff | tree
2018-12-22 whitequarkback.verilog: do not rename internal signals. commit | commitdiff | tree
2018-12-22 whitequarkcompat: fix confusing naming for memory port address... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... commit | commitdiff | tree
2018-12-22 whitequarkcompat: do not finalize native submodules twice. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide verilog.convert shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from... commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide Memory shim. commit | commitdiff | tree
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