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gem5.git
2019-02-08 Tuan Tacpu: stop scheduling suspended threads in all stages... commit | commitdiff | tree
2019-02-08 Tuan Tariscv: ignore nanosleep syscall commit | commitdiff | tree
2019-02-08 Tuan Tasim,cpu: make exit_group halt all threads in a group commit | commitdiff | tree
2019-02-08 Tuan Taarch-riscv: initialize RISC-V's thread pointer register... commit | commitdiff | tree
2019-02-08 Tuan Tasim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITS... commit | commitdiff | tree
2019-02-08 Tuan Tacpu: fixed how O3 CPU executes an exit system call commit | commitdiff | tree
2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64 commit | commitdiff | tree
2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... commit | commitdiff | tree
2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU commit | commitdiff | tree
2019-02-08 Ruben Ayrapetyanarch-arm: Fix initialization of PMU counters commit | commitdiff | tree
2019-02-07 Giacomo Travagliniconfigs, arch-arm: Using AddrRange for Realview mem_regions commit | commitdiff | tree
2019-02-07 Giacomo Travagliniconfigs: Unifiy interpretation of Realview mem_regions commit | commitdiff | tree
2019-02-07 Austin Harrisarch-riscv: Enable support for riscv 32-bit in SE mode. commit | commitdiff | tree
2019-02-06 Tuan Tariscv: remove NonSpeculative flag from fence inst commit | commitdiff | tree
2019-02-06 Tuan Tacpu: fix how a thread starts up in MinorCPU commit | commitdiff | tree
2019-02-06 Tuan Taarch-riscv: Initialize interrupt mask commit | commitdiff | tree
2019-02-06 Ciro Santilliscons: fix unused auto-generated blob variable in clang commit | commitdiff | tree
2019-02-06 Andrea Mondellisim: added missed macro definition on MacOS commit | commitdiff | tree
2019-02-05 Andrea Mondellimisc: added missing override specifier commit | commitdiff | tree
2019-02-05 Javier Buenocpu: Made the Loop Predictor a SimObject commit | commitdiff | tree
2019-02-05 Jairo Balartcpu: Made TAGE a SimObject that can be used by other... commit | commitdiff | tree
2019-02-05 Austin Harrisriscv: Get rid of ISA specific register types in Interr... commit | commitdiff | tree
2019-02-01 Javier Buenomem-cache: Updated version of the Signature Path Prefetcher commit | commitdiff | tree
2019-02-01 Anouk Van Laerdev, arm: Removed contextId variable commit | commitdiff | tree
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal. commit | commitdiff | tree
2019-01-31 Andreas Sandbergpython: Remove getCode() type workaround commit | commitdiff | tree
2019-01-31 Andreas Sandbergsim: Prepare C++ side for Python 3 commit | commitdiff | tree
2019-01-31 Andreas Sandbergtests: Add a helper to run external scripts commit | commitdiff | tree
2019-01-31 Andreas Sandbergtests: Don't override tick rate in Ruby tests commit | commitdiff | tree
2019-01-31 Gabe Blackpower: Get rid of some ISA specific register types. commit | commitdiff | tree
2019-01-31 Gabe Blacknull: Get rid of some register type definitions. commit | commitdiff | tree
2019-01-31 Gabe Blackmips: Stop using architecture specific register types. commit | commitdiff | tree
2019-01-31 Gabe Blackalpha: Stop using architecture specific register types. commit | commitdiff | tree
2019-01-31 Gabe Blackx86: Stop using/defining some ISA specific register... commit | commitdiff | tree
2019-01-31 Gabe Blackriscv: Get rid of some ISA specific register types. commit | commitdiff | tree
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*. commit | commitdiff | tree
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers commit | commitdiff | tree
2019-01-30 Giacomo Travagliniconfigs: Enable DTB autogeneration in starter_fs.py commit | commitdiff | tree
2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autoge... commit | commitdiff | tree
2019-01-28 Ciro Santillitests: fix arm regression due to kernel not found commit | commitdiff | tree
2019-01-25 Ciro Santilliconfigs: fs.py remove --generate-dtb and enable it... commit | commitdiff | tree
2019-01-25 Ciro Santilliconfigs, arch-arm: don't search for default DTB and... commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instru... commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser commit | commitdiff | tree
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the... commit | commitdiff | tree
2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64 commit | commitdiff | tree
2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models commit | commitdiff | tree
2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands commit | commitdiff | tree
2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code commit | commitdiff | tree
2019-01-25 Nicholas Lindsaypython: Always throw TypeError on slave-slave connections commit | commitdiff | tree
2019-01-24 Gabe Blackhsail: Remove the MiscReg type. commit | commitdiff | tree
2019-01-24 Gabe Blackbase: arch: Get rid of the now unused FloatRegVal type. commit | commitdiff | tree
2019-01-24 Ciro Santillidev-arm: fix --generate-dtb for ARM commit | commitdiff | tree
2019-01-24 Rekai Gonzalez... cpu-o3: O3 LSQ Generalisation commit | commitdiff | tree
2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32 commit | commitdiff | tree
2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on... commit | commitdiff | tree
2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions commit | commitdiff | tree
2019-01-23 Gabe Blacksystemc: Fix TLM related includes. commit | commitdiff | tree
2019-01-23 Gabe Blackarm: Replace MiscReg with RegVal in utility.(hh|cc). commit | commitdiff | tree
2019-01-23 Zicong Wangmem-ruby: Fix missing TBE allocation and deallocation commit | commitdiff | tree
2019-01-22 Gabe Blacksparc: Get rid of some register type definitions. commit | commitdiff | tree
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference. commit | commitdiff | tree
2019-01-22 Gabe Blackarm: Get rid of some register type definitions. commit | commitdiff | tree
2019-01-22 Gabe Blackarm: dev: Replace ArmISA::MiscReg with RegVal in the... commit | commitdiff | tree
2019-01-22 Ciro Santilliarch-arm: implement the GDB XML target description... commit | commitdiff | tree
2019-01-22 Ciro Santilliext: import GDB XML target description files for arm commit | commitdiff | tree
2019-01-22 Ciro Santilliscons: add helpers to access GDB XML description files commit | commitdiff | tree
2019-01-22 Ciro Santilliscons: allow embedding arbitrary blobs into the gem5... commit | commitdiff | tree
2019-01-22 Ciro Santillibase: add support for GDB's XML architecture definition commit | commitdiff | tree
2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers commit | commitdiff | tree
2019-01-22 Sascha Bischoffmem: Add tryTiming suppport to CommMonitor commit | commitdiff | tree
2019-01-22 Brandon Pottersim-se add readv and modifies writev commit | commitdiff | tree
2019-01-22 Brandon Pottersim-se: add ability to get/set sock metadata commit | commitdiff | tree
2019-01-22 Brandon Pottersim-se: add syscalls related to polling commit | commitdiff | tree
2019-01-22 Brandon Pottersim-se: add calls for network transmissions commit | commitdiff | tree
2019-01-22 Brandon Pottersim-se: add socket-based functionality commit | commitdiff | tree
2019-01-18 Daniel R. Carvalhobase: Fix unitialized storage commit | commitdiff | tree
2019-01-17 Gabe Blacktests: Fix tests/main.py so it can be run from anywhere. commit | commitdiff | tree
2019-01-17 Nikos Nikolerismem: Allow inserts in the begining of a packet queue commit | commitdiff | tree
2019-01-17 Nikos Nikolerismem: Determine if a packet queue forces ordering at... commit | commitdiff | tree
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtCommitPolicy a Param.ScopedEnum commit | commitdiff | tree
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtROBPolicy a Param.ScopedEnum commit | commitdiff | tree
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtIQPolicy a Param.ScopedEnum commit | commitdiff | tree
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtLSQPolicy a Param.ScopedEnum commit | commitdiff | tree
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtFetchPolicy a Param.ScopedEnum commit | commitdiff | tree
2019-01-17 Nikos Nikolerispython: Add support for scoped enums commit | commitdiff | tree
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific... commit | commitdiff | tree
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa... commit | commitdiff | tree
2019-01-16 Gabe Blackarm: Make the fp register types 64 bits. commit | commitdiff | tree
2019-01-16 Javier Buenomem-cache: Access Map Pattern Matching Prefetcher commit | commitdiff | tree
2019-01-16 Javier Buenomem-cache: Signature Path Prefetcher commit | commitdiff | tree
2019-01-16 Javier Buenomem-cache: allow prefetchers to emit page crossing... commit | commitdiff | tree
2019-01-16 Javier Buenomem-cache: virtual address support for prefetchers commit | commitdiff | tree
2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is... commit | commitdiff | tree
2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction commit | commitdiff | tree
2019-01-16 Alec Roelkearch-riscv: Add interrupt handling commit | commitdiff | tree
2019-01-16 Alec Roelkearch-riscv: Fix reset function and style commit | commitdiff | tree
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