git.libre-soc.org Git - riscv-isa-sim.git/shortlog

2010-08-04	Andrew Waterman	[sim,xcc] removed sll32/srl32/sra32 opcodes	commit \| commitdiff \| tree
2010-08-04	Andrew Waterman	[pk,sim,xcc] Renamed instructions to RISC-V spec	commit \| commitdiff \| tree
2010-07-29	Andrew Waterman	[gcc] generate code for complex branches	commit \| commitdiff \| tree
2010-07-29	Andrew Waterman	[sim,xcc] Changed instruction format to RISC-V	commit \| commitdiff \| tree
2010-07-23	Yunsup Lee	[sim] various fixes to get the sim work with the fesvr	commit \| commitdiff \| tree
2010-07-22	Andrew Waterman	[pk,sim] removed cop0 console i/o support	commit \| commitdiff \| tree
2010-07-22	Andrew Waterman	[pk,sim] first cut of appserver communication link	commit \| commitdiff \| tree
2010-07-20	Andrew Waterman	[pk,sim] added temporary "exit" functionality	commit \| commitdiff \| tree
2010-07-19	Andrew Waterman	Reorganized directory structure	commit \| commitdiff \| tree

Simple-V augmented version of spike