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yosys.git
2021-09-21
Zachary Snow
verilog: fix multiple AST_PREFIX scope resolution issues
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2021-09-19
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2021-09-18
Miodrag Milanović
Merge pull request #3010 from the6p4c/master
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2021-09-17
the6p4c
Fix protobuf backend build dependencies
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2021-09-14
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2021-09-13
Marcelina Kościelnicka
verilog: Squash flex-triggered warning.
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2021-09-13
Miodrag Milanović
Updates for CHANGELOG (#2997)
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2021-09-11
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2021-09-10
Miodrag Milanović
Merge pull request #3001 from YosysHQ/claire/sigcheck
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2021-09-10
Claire Xenia...
Add additional check to SigSpec
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2021-09-10
Marcelina Kościelnicka
yosys-smtbmc: Fix reused loop variable.
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2021-09-10
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2021-09-09
Eddie Hung
abc9: make re-entrant (#2993)
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2021-09-09
Eddie Hung
abc9: holes module to instantiate cells with NEW_ID...
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2021-09-09
Eddie Hung
abc9: replace cell type/parameters if derived type...
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2021-09-03
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2021-09-02
Miodrag Milanovic
update required verific version
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2021-09-01
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2021-08-31
Zachary Snow
sv: support declaration in generate for initialization
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2021-08-31
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2021-08-30
Zachary Snow
sv: support declaration in procedural for initialization
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2021-08-30
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2021-08-29
kittennbfive
[ECP5] fix wrong link for syn_* attributes description...
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2021-08-23
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2021-08-22
ECP5-PCIe
Add DLLDELD
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2021-08-22
Marcelina Kościelnicka
opt_merge: Remove and reinsert init when connecting...
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2021-08-22
Marcelina Kościelnicka
opt_clean: Make the init attribute follow the FF's Q.
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2021-08-21
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2021-08-20
Pepijn de Vos
Gowin: deal with active-low tristate (#2971)
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2021-08-20
Miodrag Milanović
Merge pull request #2973 from YosysHQ/micko/optional_ex...
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2021-08-20
Miodrag Milanovic
Make Verific extensions optional
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2021-08-18
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2021-08-17
Sylvain Munaut
ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
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2021-08-17
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2021-08-16
Marcelina Kościelnicka
kernel/mem: Remove old parameter when upgrading $mem...
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2021-08-15
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2021-08-14
Marcelina Kościelnicka
proc_prune: Make assign removal and promotion per-bit...
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2021-08-14
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2021-08-13
Rupert Swarbrick
Generate an RTLIL representation of bind constructs
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2021-08-13
Marcelina Kościelnicka
Add opt_mem_widen pass.
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2021-08-13
Marcelina Kościelnicka
memory_share: Add -nosat and -nowiden options.
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2021-08-13
Marcelina Kościelnicka
memory_dff: Recognize soft transparency logic.
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2021-08-13
Marcelina Kościelnicka
Add new opt_mem_priority pass.
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2021-08-13
Miodrag Milanović
Merge pull request #2932 from YosysHQ/mwk/logger-check...
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2021-08-13
Brett Witherspoon
sv: improve support for wire and var with user-defined...
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2021-08-13
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2021-08-12
Marcelina Kościelnicka
memory_share: Pass addresses through sigmap_xmux everyw...
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2021-08-12
Marcelina Kościelnicka
logger: Add -check-expected subcommand.
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2021-08-12
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2021-08-11
Marcelina Kościelnicka
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
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2021-08-11
Marcelina Kościelnicka
memory_dff: Recognize read ports with reset / initial...
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2021-08-11
Marcelina Kościelnicka
proc_memwr: Use the v2 memwr cell.
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2021-08-11
Marcelina Kościelnicka
Add v2 memory cells.
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2021-08-11
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2021-08-10
Marcelina Kościelnicka
kernel/mem: Introduce transparency masks.
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2021-08-10
Michael Singer
Allow optional comma after last entry in enum
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2021-08-10
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2021-08-09
Marcelina Kościelnicka
Refactor common parts of SAT-using optimizations into...
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2021-08-08
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2021-08-07
Marcelina Kościelnicka
opt_merge: Use FfInitVals.
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2021-08-07
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2021-08-06
Marcelina Kościelnicka
verilog: Support tri/triand/trior wire types.
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2021-08-05
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2021-08-04
Marcelina Kościelnicka
memory_share: Don't skip ports with EN wired to input...
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2021-08-04
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2021-08-03
Marcelina Kościelnicka
memory_bram: Move init data swizzling before other...
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2021-08-03
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2021-08-02
Miodrag Milanovic
Require latest verific
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2021-08-02
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2021-08-01
Marcelina Kościelnicka
backend/verilog: Add alternate mode for transparent...
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2021-08-01
Marcelina Kościelnicka
memory_bram: Some refactoring
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2021-07-31
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2021-07-30
Miodrag Milanović
Update version.yml
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2021-07-30
Maciej Dudek
Fixes xc7 BRAM36s
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2021-07-30
Zachary Snow
proc_rmdead: use explicit pattern set when there are...
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2021-07-30
Zachary Snow
genrtlil: add width detection for AST_PREFIX nodes
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2021-07-30
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2021-07-29
Marcelina Kościelnicka
opt_lut: Allow more than one -dlogic per cell type.
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2021-07-29
Zachary Snow
verilog: save and restore overwritten macro arguments
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2021-07-29
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2021-07-28
Marcelina Kościelnicka
verilog: Emit $meminit_v2 cell.
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2021-07-28
Marcelina Kościelnicka
backends/verilog: Support meminit with mask.
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2021-07-28
Marcelina Kościelnicka
memory: Introduce $meminit_v2 cell, with EN input.
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2021-07-28
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2021-07-27
Marcelina Kościelnicka
proc: Run opt_expr at the end
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2021-07-27
Marcelina Kościelnicka
opt_expr: Propagate constants to port connections.
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2021-07-27
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2021-07-26
Miodrag Milanovic
Add version bump workflow
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2021-07-21
Miodrag Milanovic
Update to latest verific
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2021-07-20
Rupert Swarbrick
Use new read_id_num helper function elsewhere in hierar...
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2021-07-20
Rupert Swarbrick
Extract connection checking logic from expand_module...
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2021-07-20
whitequark
Merge pull request #2885 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
Merge pull request #2884 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
cxxrtl: treat wires with multiple defs as not inlinable.
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2021-07-20
whitequark
cxxrtl: treat assignable internal wires used only for...
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2021-07-20
whitequark
Merge pull request #2881 from whitequark/cxxrtl-sideway...
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2021-07-19
whitequark
cxxrtl: escape colon in variable names in VCD writer.
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2021-07-18
whitequark
Merge pull request #2880 from whitequark/cxxrtl-fix...
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2021-07-18
whitequark
cxxrtl: add debug_item::{get,set}.
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2021-07-17
whitequark
Merge pull request #2879 from whitequark/cxxrtl-fix...
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