yosys.git
2021-09-21 Zachary Snowverilog: fix multiple AST_PREFIX scope resolution issues
2021-09-19 github-actions... Bump version
2021-09-18 Miodrag MilanovićMerge pull request #3010 from the6p4c/master
2021-09-17 the6p4cFix protobuf backend build dependencies
2021-09-14 github-actions... Bump version
2021-09-13 Marcelina Kościelnickaverilog: Squash flex-triggered warning.
2021-09-13 Miodrag MilanovićUpdates for CHANGELOG (#2997)
2021-09-11 github-actions... Bump version
2021-09-10 Miodrag MilanovićMerge pull request #3001 from YosysHQ/claire/sigcheck
2021-09-10 Claire Xenia... Add additional check to SigSpec
2021-09-10 Marcelina Kościelnickayosys-smtbmc: Fix reused loop variable.
2021-09-10 github-actions... Bump version
2021-09-09 Eddie Hungabc9: make re-entrant (#2993)
2021-09-09 Eddie Hungabc9: holes module to instantiate cells with NEW_ID...
2021-09-09 Eddie Hungabc9: replace cell type/parameters if derived type...
2021-09-03 github-actions... Bump version
2021-09-02 Miodrag Milanovicupdate required verific version
2021-09-01 github-actions... Bump version
2021-08-31 Zachary Snowsv: support declaration in generate for initialization
2021-08-31 github-actions... Bump version
2021-08-30 Zachary Snowsv: support declaration in procedural for initialization
2021-08-30 github-actions... Bump version
2021-08-29 kittennbfive[ECP5] fix wrong link for syn_* attributes description...
2021-08-23 github-actions... Bump version
2021-08-22 ECP5-PCIeAdd DLLDELD
2021-08-22 Marcelina Kościelnickaopt_merge: Remove and reinsert init when connecting...
2021-08-22 Marcelina Kościelnickaopt_clean: Make the init attribute follow the FF's Q.
2021-08-21 github-actions... Bump version
2021-08-20 Pepijn de VosGowin: deal with active-low tristate (#2971)
2021-08-20 Miodrag MilanovićMerge pull request #2973 from YosysHQ/micko/optional_ex...
2021-08-20 Miodrag MilanovicMake Verific extensions optional
2021-08-18 github-actions... Bump version
2021-08-17 Sylvain Munautice40: Fix typo in SB_CARRY specify for LP/UltraPlus
2021-08-17 github-actions... Bump version
2021-08-16 Marcelina Kościelnickakernel/mem: Remove old parameter when upgrading $mem...
2021-08-15 github-actions... Bump version
2021-08-14 Marcelina Kościelnickaproc_prune: Make assign removal and promotion per-bit...
2021-08-14 github-actions... Bump version
2021-08-13 Rupert SwarbrickGenerate an RTLIL representation of bind constructs
2021-08-13 Marcelina KościelnickaAdd opt_mem_widen pass.
2021-08-13 Marcelina Kościelnickamemory_share: Add -nosat and -nowiden options.
2021-08-13 Marcelina Kościelnickamemory_dff: Recognize soft transparency logic.
2021-08-13 Marcelina KościelnickaAdd new opt_mem_priority pass.
2021-08-13 Miodrag MilanovićMerge pull request #2932 from YosysHQ/mwk/logger-check...
2021-08-13 Brett Witherspoonsv: improve support for wire and var with user-defined...
2021-08-13 github-actions... Bump version
2021-08-12 Marcelina Kościelnickamemory_share: Pass addresses through sigmap_xmux everyw...
2021-08-12 Marcelina Kościelnickalogger: Add -check-expected subcommand.
2021-08-12 github-actions... Bump version
2021-08-11 Marcelina Kościelnickatest/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
2021-08-11 Marcelina Kościelnickamemory_dff: Recognize read ports with reset / initial...
2021-08-11 Marcelina Kościelnickaproc_memwr: Use the v2 memwr cell.
2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
2021-08-11 github-actions... Bump version
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-10 Michael SingerAllow optional comma after last entry in enum
2021-08-10 github-actions... Bump version
2021-08-09 Marcelina KościelnickaRefactor common parts of SAT-using optimizations into...
2021-08-08 github-actions... Bump version
2021-08-07 Marcelina Kościelnickaopt_merge: Use FfInitVals.
2021-08-07 github-actions... Bump version
2021-08-06 Marcelina Kościelnickaverilog: Support tri/triand/trior wire types.
2021-08-05 github-actions... Bump version
2021-08-04 Marcelina Kościelnickamemory_share: Don't skip ports with EN wired to input...
2021-08-04 github-actions... Bump version
2021-08-03 Marcelina Kościelnickamemory_bram: Move init data swizzling before other...
2021-08-03 github-actions... Bump version
2021-08-02 Miodrag MilanovicRequire latest verific
2021-08-02 github-actions... Bump version
2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
2021-08-01 Marcelina Kościelnickamemory_bram: Some refactoring
2021-07-31 github-actions... Bump version
2021-07-30 Miodrag MilanovićUpdate version.yml
2021-07-30 Maciej DudekFixes xc7 BRAM36s
2021-07-30 Zachary Snowproc_rmdead: use explicit pattern set when there are...
2021-07-30 Zachary Snowgenrtlil: add width detection for AST_PREFIX nodes
2021-07-30 github-actions... Bump version
2021-07-29 Marcelina Kościelnickaopt_lut: Allow more than one -dlogic per cell type.
2021-07-29 Zachary Snowverilog: save and restore overwritten macro arguments
2021-07-29 github-actions... Bump version
2021-07-28 Marcelina Kościelnickaverilog: Emit $meminit_v2 cell.
2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 github-actions... Bump version
2021-07-27 Marcelina Kościelnickaproc: Run opt_expr at the end
2021-07-27 Marcelina Kościelnickaopt_expr: Propagate constants to port connections.
2021-07-27 github-actions... Bump version
2021-07-26 Miodrag MilanovicAdd version bump workflow
2021-07-21 Miodrag MilanovicUpdate to latest verific
2021-07-20 Rupert SwarbrickUse new read_id_num helper function elsewhere in hierar...
2021-07-20 Rupert SwarbrickExtract connection checking logic from expand_module...
2021-07-20 whitequarkMerge pull request #2885 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkMerge pull request #2884 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkcxxrtl: treat wires with multiple defs as not inlinable.
2021-07-20 whitequarkcxxrtl: treat assignable internal wires used only for...
2021-07-20 whitequarkMerge pull request #2881 from whitequark/cxxrtl-sideway...
2021-07-19 whitequarkcxxrtl: escape colon in variable names in VCD writer.
2021-07-18 whitequarkMerge pull request #2880 from whitequark/cxxrtl-fix...
2021-07-18 whitequarkcxxrtl: add debug_item::{get,set}.
2021-07-17 whitequarkMerge pull request #2879 from whitequark/cxxrtl-fix...
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