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litex.git
2011-12-27
Alain Péteut
setup.py: fix to catch all modules
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2011-12-24
Alain Péteut
Add setup script
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2011-12-22
Sebastien Bourdeauducq
example: flow conversion
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2011-12-22
Sebastien Bourdeauducq
flow: sum and division actors
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2011-12-22
Sebastien Bourdeauducq
fhdl: encapsulate replicated constants
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2011-12-22
Sebastien Bourdeauducq
flow: actor class
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2011-12-22
Sebastien Bourdeauducq
csr: use optree
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2011-12-22
Sebastien Bourdeauducq
corelogic: operator tree
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2011-12-21
Sebastien Bourdeauducq
verilog: comb reset
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2011-12-21
Sebastien Bourdeauducq
verilog: break down Convert function
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2011-12-21
Sebastien Bourdeauducq
verilog: ignore variable property in combinatorial...
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2011-12-21
Sebastien Bourdeauducq
Consistent names
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2011-12-19
Sebastien Bourdeauducq
README: Flow
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2011-12-19
Sebastien Bourdeauducq
README: Core Logic, Bus, Bank
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2011-12-19
Sebastien Bourdeauducq
README: structure + FHDL description
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2011-12-18
Sebastien Bourdeauducq
examples: remove old-style declarations
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2011-12-18
Sebastien Bourdeauducq
corelogic: fix signal exports
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2011-12-18
Sebastien Bourdeauducq
fhdl: better matching of assignment
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2011-12-18
Sebastien Bourdeauducq
Remove uses of declare_signal
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2011-12-18
Sebastien Bourdeauducq
fhdl: also take into account object attributes in _make...
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2011-12-18
Sebastien Bourdeauducq
fhdl: automatic signal name from assignment
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2011-12-17
Sebastien Bourdeauducq
bank: support raw registers
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2011-12-17
Sebastien Bourdeauducq
fhdl: fix series of if/elif/else
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2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
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2011-12-17
Sebastien Bourdeauducq
verilog: get the simulator to run the combinatorial...
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2011-12-17
Sebastien Bourdeauducq
verilog: support for float parameters in instances
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2011-12-16
Sebastien Bourdeauducq
verilog: user-definable reset and clock
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2011-12-16
Sebastien Bourdeauducq
fhdl: simpler syntax
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2011-12-16
Sebastien Bourdeauducq
Pay a bit more attention to PEP8
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2011-12-13
Sebastien Bourdeauducq
wishbone2csr: wait for WB deack
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2011-12-13
Sebastien Bourdeauducq
timeline: only trigger in rest state
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2011-12-13
Sebastien Bourdeauducq
examples: Wishbone interconnect test bench
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2011-12-13
Sebastien Bourdeauducq
verilog: use blocking assignment in combinatorial process
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2011-12-13
Sebastien Bourdeauducq
wishbone: decoder: fix slave cyc generation in register...
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2011-12-12
Sebastien Bourdeauducq
wishbone2csr: fix double-write bug
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2011-12-12
Sebastien Bourdeauducq
wishbone: only send ack to the active master in arbiter
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2011-12-12
Sebastien Bourdeauducq
fhdl: allow a namespace to be specified for Verilog...
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2011-12-11
Sebastien Bourdeauducq
fhdl: support Constant parameters for Verilog conversion
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2011-12-11
Sebastien Bourdeauducq
fhdl: fix list references (thanks Lars)
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2011-12-11
Sebastien Bourdeauducq
bus: fix CSR interconnect data readback
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2011-12-11
Sebastien Bourdeauducq
bus: 14-bit CSR addresses
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2011-12-11
Sebastien Bourdeauducq
bank: fix csrgen address decoder
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2011-12-11
Sebastien Bourdeauducq
bus: Wishbone to CSR bridge
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2011-12-11
Sebastien Bourdeauducq
corelogic: timeline module
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2011-12-11
Sebastien Bourdeauducq
fhdl: remove broken fragment iadd
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2011-12-11
Sebastien Bourdeauducq
convtools: insert reset on variables
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2011-12-10
Sebastien Bourdeauducq
autofragment: remove debug
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2011-12-10
Sebastien Bourdeauducq
fhdl: autofragment
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2011-12-10
Sebastien Bourdeauducq
fhdl: fix += for empty fragment
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2011-12-10
Sebastien Bourdeauducq
fhdl: pad support in fragments
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2011-12-09
Sebastien Bourdeauducq
wishbone: decoder + shared bus interconnect
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2011-12-09
Sebastien Bourdeauducq
fhdl: replication support
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2011-12-08
Sebastien Bourdeauducq
wishbone: arbiter
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2011-12-08
Sebastien Bourdeauducq
simplebus: export GetSigName function
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2011-12-08
Sebastien Bourdeauducq
corelogic: multimux module
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2011-12-08
Sebastien Bourdeauducq
verilog: handle default in case statements
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2011-12-08
Sebastien Bourdeauducq
fhdl: improve automatic signal naming
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2011-12-08
Sebastien Bourdeauducq
Corelogic conversion example
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2011-12-08
Sebastien Bourdeauducq
corelogic: MC divider module
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2011-12-08
Sebastien Bourdeauducq
fhdl: support negation operator
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2011-12-08
Sebastien Bourdeauducq
verilog: fix unary operator conversion
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2011-12-08
Sebastien Bourdeauducq
corelogic: round-robin module
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2011-12-08
Sebastien Bourdeauducq
Named buses
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2011-12-08
Sebastien Bourdeauducq
wishbone: add missing SEL
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2011-12-08
Sebastien Bourdeauducq
instances: signal override
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2011-12-08
Sebastien Bourdeauducq
Wishbone declarations
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2011-12-08
Sebastien Bourdeauducq
Simple bus base class
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2011-12-08
Sebastien Bourdeauducq
Instance support
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2011-12-07
Sebastien Bourdeauducq
fhdl: fix implicit slice index
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2011-12-07
Sebastien Bourdeauducq
fhdl: cleanup value bv
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2011-12-05
Sebastien Bourdeauducq
Variable conversion
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2011-12-05
Sebastien Bourdeauducq
Cleanup
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2011-12-05
Sebastien Bourdeauducq
Case support + register bank generator
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2011-12-04
Sebastien Bourdeauducq
CSR bus definitions
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2011-12-04
Sebastien Bourdeauducq
Examples folder
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2011-12-04
Sebastien Bourdeauducq
Reset insertion
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2011-12-04
Sebastien Bourdeauducq
Verilog generator
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2011-12-04
Sebastien Bourdeauducq
Initial import, FHDL basic structure, divider example
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