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yosys.git
2019-04-19
Eddie Hung
Add flop support for write_xaiger
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2019-04-19
Eddie Hung
read_aiger to parse 'r' extension
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2019-04-19
Eddie Hung
Spelling
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2019-04-18
Eddie Hung
Use new -wb flag for ABC flow
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2019-04-18
Eddie Hung
write_json to not write contents (cells/wires) of white...
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2019-04-18
Eddie Hung
Ignore 'whitebox' attr in flatten with "-wb" option
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2019-04-18
Eddie Hung
Also update Makefile.inc
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2019-04-18
Eddie Hung
Make SB_LUT4 a blackbox
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2019-04-18
Eddie Hung
Fix rename
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2019-04-18
Eddie Hung
Rename to abc_*.{box,lut}
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2019-04-18
Eddie Hung
Merge remote-tracking branch 'origin/clifford/whitebox...
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2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-17
Eddie Hung
Skip if abc_box_id earlier
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2019-04-17
Eddie Hung
Remove use of abc_box_id in stat
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2019-04-17
Eddie Hung
Fix $anyseq warning and cleanup
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2019-04-17
Eddie Hung
Update Makefile.inc too
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2019-04-17
Eddie Hung
Reduce to three devices: hx, lp, u
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2019-04-17
Eddie Hung
Do not print slack histogram
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2019-04-17
Eddie Hung
Add up5k timings
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2019-04-17
Eddie Hung
Fix grammar
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2019-04-17
Eddie Hung
Update error message
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2019-04-17
Eddie Hung
Add "-device" argument to synth_ice40
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2019-04-17
Eddie Hung
Missing abc_flop_q attribute on SPRAM
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2019-04-17
Eddie Hung
Cope with inout ports
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2019-04-17
Eddie Hung
Map to SB_LUT4 from fastest input first
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2019-04-17
Eddie Hung
Working ABC9 script
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2019-04-17
Eddie Hung
Stop topological sort at abc_flop_q
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2019-04-17
Eddie Hung
Mark seq output ports with "abc_flop_q" attr
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2019-04-17
Eddie Hung
Also update Makefile.inc
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2019-04-17
Eddie Hung
synth_ice40 to use renamed files
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2019-04-17
Eddie Hung
Rename to abc.*
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2019-04-17
Eddie Hung
Revert "Try using an ICE40_CARRY_LUT primitive to avoid...
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2019-04-17
Eddie Hung
Try using an ICE40_CARRY_LUT primitive to avoid ABC...
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2019-04-17
Eddie Hung
Remove init* from xaiger, also topo-sort cells for...
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2019-04-17
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-17
Eddie Hung
Ignore a/i/o/h XAIGER extensions
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2019-04-17
Eddie Hung
Fix spacing
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2019-04-17
Clifford Wolf
Update to ABC d1b6413
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2019-04-17
Eddie Hung
Optimise
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2019-04-17
Eddie Hung
Add SB_LUT4 to box library
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2019-04-16
Eddie Hung
Add ice40 box files
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2019-04-16
Eddie Hung
abc9 to output some more info
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2019-04-16
Eddie Hung
CIs before PIs; also sort each cell's connections befor...
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2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-16
Eddie Hung
Port from xc7mux branch
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2019-04-16
Eddie Hung
Re-enable partsel.v test
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2019-04-16
Eddie Hung
abc9 to call "setundef -zero" behaving as for abc
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2019-04-16
Eddie Hung
Merge pull request #939 from YosysHQ/revert895
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2019-04-16
Eddie Hung
Revert #895
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2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-16
Eddie Hung
Merge pull request #937 from YosysHQ/revert-932-eddie...
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2019-04-16
Eddie Hung
Revert "Recognise default entry in case even if all...
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2019-04-15
Eddie Hung
Merge pull request #936 from YosysHQ/README-fix-quotes
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2019-04-15
whitequark
README: fix some incorrect quoting.
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2019-04-13
Eddie Hung
Forgot backslashes
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2019-04-13
Eddie Hung
Handle __dummy_o__ and __const[01]__ in read_aiger...
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2019-04-13
Eddie Hung
abc to ignore __dummy_o__ and __const[01]__ when re...
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2019-04-13
Eddie Hung
Output __const0__ and __const1__ CIs
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2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-13
Eddie Hung
Fix inout handling for -map option
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2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Use -map instead of -symbols for aiger
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2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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2019-04-12
Eddie Hung
Also cope with duplicated CIs
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2019-04-12
Eddie Hung
WIP
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2019-04-12
Eddie Hung
Comment out
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2019-04-12
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-12
Eddie Hung
Cope with an output having same name as an input (i...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Keith Rothman
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12
Clifford Wolf
Merge pull request #933 from dh73/master
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2019-04-12
Clifford Wolf
Merge pull request #932 from YosysHQ/eddie/fixdlatch
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2019-04-12
Diego
Fixing issues in CycloneV cell sim
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases cover...
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2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
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2019-04-10
Eddie Hung
parse_aiger() to rename all $lut cells after "clean"
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2019-04-09
Keith Rothman
Fix LUT6_2 definition.
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2019-04-09
Keith Rothman
Add additional cells sim models for core 7-series prima...
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2019-04-08
Eddie Hung
Fix a few typos
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2019-04-08
Eddie Hung
More space fixing
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2019-04-08
Eddie Hung
Fix spacing
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-08
Clifford Wolf
Merge pull request #919 from YosysHQ/multiport_transp
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2019-04-07
David Shah
memory_bram: Fix multiport make_transp
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2019-04-05
Clifford Wolf
Add "read_ilang -lib"
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2019-04-04
Clifford Wolf
Added missing argument checking to "mutate" command
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Sylvain Munaut
proc_mux: Fix crash when trying to optimize non-existan...
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2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
David Shah
memory_bram: Consider read enable for address expansion...
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
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2019-03-29
Clifford Wolf
Merge pull request #907 from YosysHQ/clifford/fix906
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2019-03-29
Clifford Wolf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes...
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2019-03-28
Clifford Wolf
Merge pull request #901 from trcwm/libertyfixes
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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