projects
/
yosys.git
/ shortlog
commit
grep
author
committer
pickaxe
?
search:
re
summary
| shortlog |
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅
next
yosys.git
2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
commit
|
commitdiff
|
tree
2018-10-24
Udi Finkelstein
Rename the generic "Syntax error" message from the...
commit
|
commitdiff
|
tree
2018-10-23
Clifford Wolf
Merge pull request #677 from daveshah1/ecp5_dsp
commit
|
commitdiff
|
tree
2018-10-22
David Shah
ecp5: Remove DSP parameters that don't work
commit
|
commitdiff
|
tree
2018-10-21
David Shah
ecp5: Add DSP blackboxes
commit
|
commitdiff
|
tree
2018-10-20
Clifford Wolf
Improve read_verilog range out of bounds warning
commit
|
commitdiff
|
tree
2018-10-20
Clifford Wolf
Merge pull request #674 from rubund/feature/svinterface...
commit
|
commitdiff
|
tree
2018-10-20
Ruben Undheim
Refactor code to avoid code duplication + added comments
commit
|
commitdiff
|
tree
2018-10-20
Ruben Undheim
Support for SystemVerilog interfaces as a port in the...
commit
|
commitdiff
|
tree
2018-10-20
Ruben Undheim
Fixed memory leak
commit
|
commitdiff
|
tree
2018-10-19
Clifford Wolf
Merge pull request #673 from daveshah1/ecp5_improve
commit
|
commitdiff
|
tree
2018-10-19
David Shah
ecp5: Sim model fixes
commit
|
commitdiff
|
tree
2018-10-19
David Shah
ecp5: Add latch inference
commit
|
commitdiff
|
tree
2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
commit
|
commitdiff
|
tree
2018-10-19
David Shah
memory_bram: Reset make_outreg when growing read ports
commit
|
commitdiff
|
tree
2018-10-19
Clifford Wolf
Merge pull request #671 from rafaeltp/master
commit
|
commitdiff
|
tree
2018-10-19
Clifford Wolf
Merge pull request #670 from rubund/feature/basic_svint...
commit
|
commitdiff
|
tree
2018-10-18
rafaeltp
adding offset info to memories
commit
|
commitdiff
|
tree
2018-10-18
rafaeltp
adding offset info to memories
commit
|
commitdiff
|
tree
2018-10-18
Ruben Undheim
Basic test for checking correct synthesis of SystemVeri...
commit
|
commitdiff
|
tree
2018-10-18
Clifford Wolf
Update ABC to git rev 14d985a
commit
|
commitdiff
|
tree
2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
commit
|
commitdiff
|
tree
2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
commit
|
commitdiff
|
tree
2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Update ABC to git rev c5b48bb
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Minor code cleanups in liberty front-end
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Merge pull request #658 from daveshah1/ecp5_bram
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Merge pull request #641 from tklam/master
commit
|
commitdiff
|
tree
2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
commit
|
commitdiff
|
tree
2018-10-16
Clifford Wolf
We have 2018 now
commit
|
commitdiff
|
tree
2018-10-16
Clifford Wolf
After release is before release
commit
|
commitdiff
|
tree
2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
commit
|
commitdiff
|
tree
2018-10-16
Clifford Wolf
Yosys 0.8
yosys-0.8
commit
|
commitdiff
|
tree
2018-10-16
argama
ignore protect endprotect
commit
|
commitdiff
|
tree
2018-10-16
Clifford Wolf
Update command reference manual
commit
|
commitdiff
|
tree
2018-10-16
David Shah
ecp5: Disable LSR inversion
commit
|
commitdiff
|
tree
2018-10-15
Aman Goel
Minor update
commit
|
commitdiff
|
tree
2018-10-13
Ruben Undheim
Handle FIXME for modport members without type directly...
commit
|
commitdiff
|
tree
2018-10-13
Ruben Undheim
Documentation improvements etc.
commit
|
commitdiff
|
tree
2018-10-13
argama
detect ff/latch before processing other nodes
commit
|
commitdiff
|
tree
2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
commit
|
commitdiff
|
tree
2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
commit
|
commitdiff
|
tree
2018-10-13
tklam
Merge branch 'master' of https://github.com/YosysHQ...
commit
|
commitdiff
|
tree
2018-10-12
Ruben Undheim
Fix build error with clang
commit
|
commitdiff
|
tree
2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
commit
|
commitdiff
|
tree
2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
commit
|
commitdiff
|
tree
2018-10-12
David Shah
BRAM improvements
commit
|
commitdiff
|
tree
2018-10-10
David Shah
ecp5: Adding BRAM maps for all size options
commit
|
commitdiff
|
tree
2018-10-10
David Shah
ecp5: First BRAM type maps successfully
commit
|
commitdiff
|
tree
2018-10-10
David Shah
ecp5: Script for BRAM IO connections
commit
|
commitdiff
|
tree
2018-10-09
David Shah
ecp5: Adding BRAM initialisation and config
commit
|
commitdiff
|
tree
2018-10-08
Tim 'mithro...
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
commit
|
commitdiff
|
tree
2018-10-07
Clifford Wolf
Improve Verific importer blackbox handling
commit
|
commitdiff
|
tree
2018-10-05
David Shah
ecp5: Add blackbox for DP16KD
commit
|
commitdiff
|
tree
2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
commit
|
commitdiff
|
tree
2018-10-05
Clifford Wolf
Add "write_edif -attrprop"
commit
|
commitdiff
|
tree
2018-10-05
Clifford Wolf
Merge pull request #654 from mithro/patch-1
commit
|
commitdiff
|
tree
2018-10-05
Clifford Wolf
Fix compiler warning in verific.cc
commit
|
commitdiff
|
tree
2018-10-05
Tim Ansell
Fix misspelling in issue_template.md
commit
|
commitdiff
|
tree
2018-10-04
Adrian Wheeldon
Fix IdString M in setup_stdcells()
commit
|
commitdiff
|
tree
2018-10-04
Clifford Wolf
Add inout ports to cells_xtra.v
commit
|
commitdiff
|
tree
2018-10-04
Clifford Wolf
Merge pull request #650 from mithro/patch-1
commit
|
commitdiff
|
tree
2018-10-03
Tim Ansell
xilinx: Adding missing inout IO port to IOBUF
commit
|
commitdiff
|
tree
2018-10-03
tklam
Merge branch 'master' of https://github.com/YosysHQ...
commit
|
commitdiff
|
tree
2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
commit
|
commitdiff
|
tree
2018-10-02
Clifford Wolf
Merge pull request #646 from tomverbeure/issue594
commit
|
commitdiff
|
tree
2018-10-02
Tom Verbeure
Fix for issue 594.
commit
|
commitdiff
|
tree
2018-10-01
Aman Goel
Update to .smv backend
commit
|
commitdiff
|
tree
2018-10-01
Dan Gisselquist
Add read_verilog $changed support
commit
|
commitdiff
|
tree
2018-10-01
David Shah
ecp5: Don't map ROMs to DRAM
commit
|
commitdiff
|
tree
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
commit
|
commitdiff
|
tree
2018-09-30
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
commit
|
commitdiff
|
tree
2018-09-30
Clifford Wolf
Fix handling of $past 2nd argument in read_verilog
commit
|
commitdiff
|
tree
2018-09-28
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
commit
|
commitdiff
|
tree
2018-09-28
Clifford Wolf
Update to v2 YosysVS template
commit
|
commitdiff
|
tree
2018-09-26
tklam
fix bug: pass by reference
commit
|
commitdiff
|
tree
2018-09-26
TK Lam
Fix issue #639
commit
|
commitdiff
|
tree
2018-09-24
Udi Finkelstein
Fixed issue #630 by fixing a minor typo in the previous...
commit
|
commitdiff
|
tree
2018-09-24
Clifford Wolf
Add "read_verilog -noassert -noassume -assert-assumes"
commit
|
commitdiff
|
tree
2018-09-23
Clifford Wolf
Added support for ommited "parameter" in Verilog-2001...
commit
|
commitdiff
|
tree
2018-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/mmicko...
commit
|
commitdiff
|
tree
2018-09-23
Clifford Wolf
Update CHANGELOG
commit
|
commitdiff
|
tree
2018-09-21
Miodrag Milanovic
added prefix to FDirection constants, fixing windows...
commit
|
commitdiff
|
tree
2018-09-21
Clifford Wolf
Update CHANGLELOG
commit
|
commitdiff
|
tree
2018-09-21
Clifford Wolf
Update Changelog
commit
|
commitdiff
|
tree
2018-09-19
Clifford Wolf
Merge pull request #633 from mmicko/master
commit
|
commitdiff
|
tree
2018-09-19
Clifford Wolf
Merge pull request #631 from acw1251/master
commit
|
commitdiff
|
tree
2018-09-19
Miodrag Milanovic
Fix Cygwin build and document needed packages
commit
|
commitdiff
|
tree
2018-09-18
acw1251
Fixed typo in "verilog_write" help message
commit
|
commitdiff
|
tree
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
commit
|
commitdiff
|
tree
2018-09-17
Udi Finkelstein
Fixed remaining cases where we check fo wire reg/wire...
commit
|
commitdiff
|
tree
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
commit
|
commitdiff
|
tree
2018-09-14
Clifford Wolf
Merge pull request #627 from acw1251/master
commit
|
commitdiff
|
tree
2018-09-12
acw1251
Fixed minor typo in "sim" help message
commit
|
commitdiff
|
tree
2018-09-11
Aman Goel
Minor revision to -expose in setundef pass
commit
|
commitdiff
|
tree
2018-09-10
Clifford Wolf
Add iCE40 SB_SPRAM256KA simulation model
commit
|
commitdiff
|
tree
2018-09-05
Clifford Wolf
Add $lut support to Verilog back-end
commit
|
commitdiff
|
tree
2018-09-04
Clifford Wolf
Add "verific -L <int>" option
commit
|
commitdiff
|
tree
next