yosys.git
2019-08-03 Miodrag MilanovicCustom step to add global clock buffers
2019-08-03 Miodrag MilanovicInitial EFINIX support
2019-08-02 Clifford WolfMerge pull request #1238 from mmicko/vsbuild_fix
2019-08-02 Clifford WolfMerge pull request #1239 from mmicko/mingw_fix
2019-08-01 Eddie HungMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
2019-08-01 Miodrag MilanovicFix linking issue for new mxe and pthread
2019-08-01 Miodrag MilanovicFix yosys linking for mxe
2019-08-01 Miodrag MilanovicNew mxe hacks needed to support 2ca237e
2019-08-01 Miodrag MilanovicFix formatting for msys2 mingw build using GetSize
2019-07-31 Clifford WolfMerge pull request #1233 from YosysHQ/clifford/defer
2019-07-31 Miodrag MilanovicVisual Studio build fix
2019-07-29 Eddie HungRST -> RSTBRST for RAMB8BWER
2019-07-29 Eddie HungMerge pull request #1228 from YosysHQ/dave/yy_buf_size
2019-07-29 David ShahMerge pull request #1234 from mmicko/fix_gzip_no_exist
2019-07-29 Miodrag MilanovicFix case when file does not exist
2019-07-29 Clifford WolfUpdate README to use "read" instead of "read_verilog"
2019-07-29 Clifford WolfCall "read_verilog" with -defer from "read"
2019-07-27 David ShahMerge pull request #1226 from YosysHQ/dave/gzip
2019-07-26 David ShahUpdate CHANGELOG
2019-07-26 David Shahverilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 David ShahFix frontend auto-detection for gzipped input
2019-07-26 David ShahAdd support for reading gzip'd input files
2019-07-25 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-07-25 Eddie HungBump abc to fix &mfs bug
2019-07-25 Clifford WolfMerge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 Clifford WolfMerge pull request #1218 from ZirconiumX/synth_intel_iopads
2019-07-25 Clifford WolfMerge pull request #1219 from jakobwenzel/objIterator
2019-07-25 Eddie HungMerge pull request #1224 from YosysHQ/xilinx_fix_ff
2019-07-25 Jakob Wenzelreplaced std::iterator with using statements
2019-07-25 David Shahxilinx: Fix missing cell name underscore in cells_map.v
2019-07-24 Eddie HungMerge pull request #1222 from koriakin/s6-example
2019-07-24 Marcin KoƛcielnickiAdd a simple example for Spartan 6
2019-07-24 Jakob Wenzelmade ObjectIterator extend std::iterator
2019-07-24 Dan Ravensloftintel: Make -noiopads the default
2019-07-23 Dan Ravensloftintel: Map M9K BRAM only on families that have it
2019-07-23 Eddie HungMerge pull request #1212 from YosysHQ/eddie/signed_ice4...
2019-07-22 Eddie HungMerge pull request #1214 from jakobwenzel/astmod_clone
2019-07-22 Jakob Wenzelinitialize noblackbox and nowb in AstModule::clone
2019-07-20 Clifford WolfAdd "stat -tech cmos"
2019-07-19 David Shahice40: Fix test_dsp_model.sh
2019-07-19 David Shahice40/cells_sim.v: Fix sign of J and K partial products
2019-07-19 David Shahice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
2019-07-19 Eddie HungAdd tests for all combinations of A and B signedness...
2019-07-19 Eddie HungDon't copy ref if exists already
2019-07-18 David ShahMerge pull request #1208 from ZirconiumX/intel_cleanups
2019-07-18 Dan Ravensloftsynth_intel: Use stringf
2019-07-18 David ShahMerge pull request #1207 from ZirconiumX/intel_new_pass...
2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/
2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10
2019-07-18 Ben Widawskyintel_synth: Fix help message
2019-07-18 Ben Widawskyintel_synth: Small code cleanup to remove if ladder
2019-07-18 Ben Widawskyintel_synth: Make family explicit and match
2019-07-18 Ben Widawskyintel_synth: Minor code cleanups
2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184
2019-07-18 Clifford WolfMerge pull request #1184 from whitequark/synth-better...
2019-07-18 Clifford WolfMerge pull request #1203 from whitequark/write_verilog...
2019-07-17 Clifford WolfRemove old $pmux_safe code from write_verilog
2019-07-17 David ShahMerge pull request #1204 from smunaut/fix_1187
2019-07-16 Sylvain Munautice40: Adapt the relut process passes to the new $lut...
2019-07-16 whitequarkwrite_verilog: dump zero width constants correctly.
2019-07-16 Eddie HungMerge pull request #1202 from YosysHQ/cmp2lut_lut6
2019-07-16 whitequarksynth_ecp5: rename dram to lutram everywhere.
2019-07-16 whitequarksynth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 Eddie Hunggen_lut to return correctly sized LUT mask
2019-07-16 Eddie HungForgot to commit
2019-07-16 Eddie HungAdd tests for cmp2lut on LUT6
2019-07-16 Eddie HungMerge pull request #1188 from YosysHQ/eddie/abc9_push_i...
2019-07-16 Eddie HungMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
2019-07-16 Clifford WolfMerge pull request #1200 from mmicko/fix_typo_liberty_cc
2019-07-16 Clifford WolfMerge pull request #1199 from mmicko/extract_fa_fix
2019-07-16 Miodrag MilanovicFix typo, double "of"
2019-07-16 Miodrag MilanovicFix check logic in extract_fa
2019-07-15 Eddie HungMerge pull request #1196 from YosysHQ/eddie/fix1178
2019-07-15 Eddie Hung$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per ...
2019-07-15 Clifford WolfMerge pull request #1189 from YosysHQ/eddie/fix1151
2019-07-15 Clifford WolfMerge pull request #1190 from YosysHQ/eddie/fix_1099
2019-07-15 Clifford WolfMerge pull request #1191 from whitequark/opt_lut-log_debug
2019-07-15 Clifford WolfMerge pull request #1195 from Roman-Parise/master
2019-07-15 Clifford WolfMerge pull request #1197 from nakengelhardt/handle...
2019-07-15 Eddie HungRevert "Add log_checkpoint function and use it in opt_m...
2019-07-15 N. Engelhardtsmt: handle failure of setrlimit syscall
2019-07-15 Eddie HungRevert "Fix first divergence in #1178"
2019-07-15 Eddie HungMerge branch 'master' into eddie/fix1178
2019-07-15 Clifford WolfRedesign log_id_cache so that it doesn't keep IdString...
2019-07-15 Clifford WolfAdd log_checkpoint function and use it in opt_muxtree
2019-07-14 Eddie HungMerge pull request #1194 from cr1901/miss-semi
2019-07-14 William D.... Fix missing semicolon in Windows-specific code in aiger...
2019-07-14 Roman-PariseUpdated FreeBSD dependencies in README.md
2019-07-13 whitequarkopt_lut: make less chatty.
2019-07-13 Eddie HungIf ConstEval fails do not log_abort() but return gracefully
2019-07-13 Eddie HungError out if enable > dbits
2019-07-13 Eddie Hungice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 Eddie HungAdd comment
2019-07-13 Eddie HungUpdate test with more accurate LUT mask
2019-07-13 Eddie Hungduplicate -> clone
2019-07-13 Eddie HungMore cleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungMore cleanup
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