| 2018-12-22 | whitequark | back.verilog: do not rename internal signals. | commit | commitdiff | tree | 
| 2018-12-22 | whitequark | compat: fix confusing naming for memory port address... | commit | commitdiff | tree | 
| 2018-12-22 | whitequark | hdl.ir: fix port propagation between siblings, in the... | commit | commitdiff | tree | 
| 2018-12-22 | whitequark | compat: do not finalize native submodules twice. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: use more informative signal naming for ports. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.ir: fix port propagation between siblings. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | compat: provide verilog.convert shim. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.ir: do not flatten instances or collect ports from... | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | compat: provide Memory shim. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: ensure transparent read port model has correct... | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.pysim: handle out of bounds ArrayProxy indexes. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.pysim: give numeric names to unnamed subfragments... | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: use different naming for array signals. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: add simulation model for memory. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.pysim: fix an issue with too few funclet slots. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: add tests for all error conditions. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.rtlil: more consistent prefixing for subfragment... | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.ir: correctly handle named output and inout ports. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.rtlil: implement memories. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | hdl.mem: implement memories. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.rtlil: explicitly pad constants with zeroes. | commit | commitdiff | tree | 
| 2018-12-21 | whitequark | back.rtlil: fix translation of Cat. | commit | commitdiff | tree | 
| 2018-12-20 | whitequark | ir: allow non-Signals in Instance ports. | commit | commitdiff | tree | 
| 2018-12-19 | whitequark | setup: update pyvcd dependency, for var_type="string". | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | compat: import genlib.record from Migen. | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy... | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | hdl.ast: Cat.{operands→parts} | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: implement *. | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | test.sim: add tests for sync functionality and errors. | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: eliminate most dictionary lookups. | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | hdl.ast, hdl.xfrm: various microoptimizations to speed... | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: use arrays instead of dicts for signal... | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: naming. NFC. | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: fix an off-by-1 in add_sync_process(). | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: trigger processes waiting on Tick() exactly... | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | back.pysim: continue running simulator processes until... | commit | commitdiff | tree | 
| 2018-12-18 | whitequark | Travis: cache Yosys installation explicitly. | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | fhdl.ir: add black-box fragments, fragment parameters... | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | Travis: build and cache Yosys. | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | hdl, back: add and use SignalSet/SignalDict. | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | hdl.ast: factor out _MappedKeyDict, _MappedKeySet.... | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | back.rtlil: update for Yosys master. | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | back.rtlil: implement Array. | commit | commitdiff | tree | 
| 2018-12-17 | whitequark | back.rtlil: implement Part. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: handle reset_less domains. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | hdl.dsl: add clock domain support. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | hdl.dsl: cleanup. NFC. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: extract _StatementCompiler. NFC. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: simplify. NFC. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: properly escape strings in attributes. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | README: mention Yosys requirement. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: prepare for Yosys sigspec slicing improvements. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | compat.fhdl.structure: only convert to bool in If/Elif... | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: avoid illegal slices. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: use slicing to match shape when reducing... | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: don't emit a slice if all bits are used. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: reorganize value compiler into LHS/RHS. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.rtlil: fix naming. NFC. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | hdl.xfrm: separate AST traversal from AST identity... | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | compat.fhdl: reexport Array. | commit | commitdiff | tree | 
| 2018-12-16 | whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | test.sim: generalize assertOperator. NFC. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | back.pysim: add (stub) LHSValueCompiler. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | back.pysim: implement Part. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | examples: rename clkdiv/ctrl to ctr/ctr_ce. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | doc: update COMPAT_SUMMARY. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | back.pysim: implement ArrayProxy. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | hdl.ast: implement Array and ArrayProxy. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | Lower Python version requirement to 3.6. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | hdl: appropriately rename tests. NFC. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | hdl.ast: improve ClockSignal, ResetSignal documentation. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | Rename fhdl→hdl, genlib→lib. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | Move star imports to make `from nmigen import *` usable. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | doc: fix some Markdown awkwardness. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | doc: update COMPAT_SUMMARY to reflect actual status. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | Determine Migen's API surface and document compatibilit... | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | pyback.sim: test Slice, Cat, Repl. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | fhdl.ast, back.pysim: implement shifts. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | fhdl.ast: refactor Operator.shape(). NFC. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | Consistently use '{!r}' in and only in TypeError messages. | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | fhdl.ir: fix incorrect uses of positive to say non... | commit | commitdiff | tree | 
| 2018-12-15 | whitequark | compat.fhdl.structure: handle If/Elif with multi-bit... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | compat.fhdl.module: allow adding native submodules... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | Fix deprecations in Python 3.7. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: preserve process locations through add_sync... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | fhdl.ast: clean up stub error messages. NFC. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | fhdl.ir: automatically flatten hierarchy to resolve... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | fhdl.ir: Fragment.{drive→add_driver} | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: count delta cycles separately to avoid... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: simplify. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: revert 70ebc6f2. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: fix implicit boolean conversion. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: squash one level of hierarchy. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: implement blocking assignment semantics... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: undriven sync signals should return to... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: in simulator sync processes, start by waiti... | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | back.pysim: make initial phase configurable. | commit | commitdiff | tree | 
| 2018-12-14 | whitequark | compat.sim: match clock period. | commit | commitdiff | tree | 
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