| 2022-01-05 |
Dmitry Selyutin | sv_binutils: introduce code generator class |
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| 2022-01-05 |
Dmitry Selyutin | sv_binutils: use stdin as input stream |
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| 2022-01-05 |
Dmitry Selyutin | sv_binutils: introduce helper classes |
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| 2022-01-03 |
Luke Kenneth... | copy over msr and rename cia to nia in PowerDecoder2 |
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| 2021-12-28 |
Cesar Strauss | Add an inorder flag to pspec |
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| 2021-12-27 |
Luke Kenneth... | add empty default_mem for running without MMU |
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| 2021-12-27 |
Luke Kenneth... | whoops wrong parameter name |
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| 2021-12-27 |
Luke Kenneth... | quick attempt to fix test_decoder_gas.py (did not work) |
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| 2021-12-27 |
Mikolaj Wielgus | bool() is !!() for integers |
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| 2021-12-27 |
Mikolaj Wielgus | Add missing parentheses for explicit operator precedence |
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| 2021-12-26 |
Luke Kenneth... | add very basic PowerDecode2 test which at least gets... |
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| 2021-12-26 |
Luke Kenneth... | a few extra things discovered needing c syntax not... |
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| 2021-12-26 |
Mikolaj Wielgus | Give human-readable names to slots, run functions and... |
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| 2021-12-25 |
Mikolaj Wielgus | Put CRTL CFFI modules in crtl dir |
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| 2021-12-25 |
Dmitry Selyutin | sv_binutils: provide small comment on regex |
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| 2021-12-25 |
Dmitry Selyutin | sv_binutils: introduce entry dataclass |
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| 2021-12-24 |
Luke Kenneth... | clear memory is optional |
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| 2021-12-24 |
Luke Kenneth... | whoops forgot to put the copy of the wb_get memory... |
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| 2021-12-23 |
Luke Kenneth... | code cleanup / comments |
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| 2021-12-23 |
Luke Kenneth... | repeat power decode test to check performance |
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| 2021-12-23 |
Luke Kenneth... | bit of a tidyup of crtl: |
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| 2021-12-23 |
Luke Kenneth... | add load-store byte-reverse 64-bit unit test |
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| 2021-12-23 |
Mikolaj Wielgus | Add CRTL templates |
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| 2021-12-23 |
Mikolaj Wielgus | Give unique names to CRTL-generated modules |
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| 2021-12-23 |
Mikolaj Wielgus | Move "pending" set to C |
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| 2021-12-22 |
Mikolaj Wielgus | Make _PySignalState CRTL-aware |
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| 2021-12-21 |
Luke Kenneth... | take a copy of the wb_get memory and then for each... |
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| 2021-12-21 |
Luke Kenneth... | ISACaller (actually RADIXMMU) only do virtual memory... |
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| 2021-12-20 |
Mikolaj Wielgus | Generate variable declaration in some missing places |
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| 2021-12-20 |
Luke Kenneth... | create header/footer for crtl code-generation |
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| 2021-12-20 |
Luke Kenneth... | whoops forgot to trap if non-execute (instruction)... |
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| 2021-12-19 |
Luke Kenneth... | TODO notes for executing ISACaller Invalid Instruction... |
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| 2021-12-19 |
Luke Kenneth... | pass the mode (LOAD,EXECUTE,STORE) through ISACaller... |
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| 2021-12-19 |
Luke Kenneth... | add "stop at pc" argument to TestCase, |
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| 2021-12-19 |
Dmitry Selyutin | sv/binutils.py: provide sketch sv_decode.vhdl converter |
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| 2021-12-19 |
Luke Kenneth... | save mmu simulation to different gtkwave file in TestRu... |
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| 2021-12-18 |
Luke Kenneth... | bit more verbose info about number of instructions run |
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| 2021-12-18 |
Luke Kenneth... | use new core domain variable in TestRunnerBase |
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| 2021-12-18 |
Luke Kenneth... | update comments in wb_get |
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| 2021-12-18 |
Luke Kenneth... | ooo annoying, it is actually icache.ibus |
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| 2021-12-18 |
Luke Kenneth... | whoops error in accessing icache.ibus which is an inter... |
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| 2021-12-17 |
Mikolaj Wielgus | Call the simulator-generated C using the CFFI |
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| 2021-12-16 |
Luke Kenneth... | bug where t1 was set to zero but s2 was not in imdct36_... |
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| 2021-12-16 |
Luke Kenneth... | start/stop wb_get in TestRunnerBase, otherwise it never... |
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| 2021-12-15 |
Luke Kenneth... | must read off of ibus in wb_get TestRunnerBase |
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| 2021-12-14 |
Mikolaj Wielgus | Add CFFI as dependency |
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| 2021-12-13 |
Tobias Platen | add namedtuple MSRSpec |
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| 2021-12-12 |
Luke Kenneth... | copy over fake OP_FETCH_FAILED and instruction on... |
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| 2021-12-12 |
Luke Kenneth... | enable mmu_cache_wb for wb_get mode in TestRunnerBase |
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| 2021-12-12 |
Luke Kenneth... | add pretty-print of MMU memory to be used for a TestRun... |
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| 2021-12-11 |
Luke Kenneth... | remove ROTL64(1, idx), just use TLI[7-idx] it is shorte... |
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| 2021-12-11 |
Luke Kenneth... | use concat in ternlogi to reduce code size |
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| 2021-12-10 |
Jacob Lifshay | add ternlogi to SVP64Asm |
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| 2021-12-10 |
Jacob Lifshay | format code |
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| 2021-12-10 |
Jacob Lifshay | change ternlogi to not have Rc field |
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| 2021-12-10 |
Jacob Lifshay | add .gitignore to ignore the generated vhdl |
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| 2021-12-09 |
Luke Kenneth... | add I-Cache wishbone bus to wb_get when MMU and ROM... |
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| 2021-12-09 |
Luke Kenneth... | add warning about creation of "-.csv" which indicates... |
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| 2021-12-09 |
Luke Kenneth... | add FAST SPRs temporarily to power_enums |
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| 2021-12-09 |
Jacob Lifshay | make ternlogi tests run |
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| 2021-12-09 |
Jacob Lifshay | rename ternaryi to ternlogi |
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| 2021-12-09 |
Jacob Lifshay | add initial ternlogi pseudo-code |
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| 2021-12-08 |
Luke Kenneth... | add instr_fault to PowerDecoder2 |
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| 2021-12-08 |
Luke Kenneth... | whitespace |
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| 2021-12-08 |
Luke Kenneth... | code-comments for LDSTException.instr_fault |
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| 2021-12-08 |
Luke Kenneth... | add an on_Display function which is being used by some... |
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| 2021-12-08 |
Luke Kenneth... | found a way to print out the names of the signals |
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| 2021-12-08 |
Luke Kenneth... | absolute import again |
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| 2021-12-08 |
Luke Kenneth... | use full-path imports (so we know where they come from) |
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| 2021-12-08 |
Mikolaj Wielgus | WIP: Output C instead of Python for Nmigen simulation |
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| 2021-12-08 |
Mikolaj Wielgus | Source Nmigen simulator from this repository |
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| 2021-12-07 |
Luke Kenneth... | whoops wrong number |
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| 2021-12-07 |
Luke Kenneth... | add OP_FETCH_FAILED micro-op |
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| 2021-12-07 |
Jacob Lifshay | fix broken url |
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| 2021-12-05 |
Tobias Platen | fix microwatt_mmu and and wishbone_memory output in... |
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| 2021-12-05 |
Luke Kenneth... | connect to dcache.bus standard interface when using... |
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| 2021-12-05 |
Luke Kenneth... | correct import of wb_get function |
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| 2021-12-04 |
Luke Kenneth... | add name parameter to wb_get |
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| 2021-12-04 |
Luke Kenneth... | add wb_get function for emulating wishbone interface |
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| 2021-12-04 |
Luke Kenneth... | raise a MemException in ISACaller RADIXMMU |
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| 2021-12-04 |
Luke Kenneth... | enable MMU in SimRunner if requested. now HDL and... |
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| 2021-12-04 |
Luke Kenneth... | test in SimState for access to RADIX memory, bypass... |
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| 2021-12-03 |
Luke Kenneth... | add a namedtuple LDSTExceptionTuple which allows obtaining |
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| 2021-12-03 |
Luke Kenneth... | add link to exceptions in gtkw traces |
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| 2021-12-02 |
Luke Kenneth... | regspec_decode_write now stores the decoded write info... |
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| 2021-12-02 |
Luke Kenneth... | specify length in RegDecodeInfo explicitly so that... |
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| 2021-12-02 |
Luke Kenneth... | use namedtuple in get_rdflags |
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| 2021-12-02 |
Luke Kenneth... | use namedtuple for regspec_decode |
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| 2021-12-02 |
Luke Kenneth... | add module to regspec_decode_* and get_rdflags |
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| 2021-12-02 |
Jacob Lifshay | move ternlogi to SHIFT_ROT unit |
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| 2021-12-02 |
Jacob Lifshay | fix sv_analysis command, cuz script created by setup... |
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| 2021-12-02 |
Jacob Lifshay | format code |
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| 2021-12-01 |
Luke Kenneth... | fix expected state in hazard test |
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| 2021-12-01 |
Luke Kenneth... | fix expected state in hazard case_regression_1 |
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| 2021-12-01 |
Luke Kenneth... | add a proper twin addi regression which tests Reservati... |
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| 2021-12-01 |
Luke Kenneth... | add regspec_decode which takes readmode arg and returns... |
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| 2021-11-30 |
Dmitry Selyutin | sv_analysis: decouple declarations and definitions |
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| 2021-11-30 |
Dmitry Selyutin | sv_analysis: use is instead of eq for enums |
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| 2021-11-30 |
Dmitry Selyutin | sv_analysis: fix single-line binutils comments |
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| 2021-11-30 |
Luke Kenneth... | add randomised hazard test |
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