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openpower-isa.git
2021-12-08
Luke Kenneth...
absolute import again
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2021-12-08
Luke Kenneth...
use full-path imports (so we know where they come from)
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2021-12-08
Mikolaj Wielgus
WIP: Output C instead of Python for Nmigen simulation
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2021-12-08
Mikolaj Wielgus
Source Nmigen simulator from this repository
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2021-12-07
Luke Kenneth...
whoops wrong number
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2021-12-07
Luke Kenneth...
add OP_FETCH_FAILED micro-op
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2021-12-07
Jacob Lifshay
fix broken url
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2021-12-05
Tobias Platen
fix microwatt_mmu and and wishbone_memory output in...
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2021-12-05
Luke Kenneth...
connect to dcache.bus standard interface when using...
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2021-12-05
Luke Kenneth...
correct import of wb_get function
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2021-12-04
Luke Kenneth...
add name parameter to wb_get
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2021-12-04
Luke Kenneth...
add wb_get function for emulating wishbone interface
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2021-12-04
Luke Kenneth...
raise a MemException in ISACaller RADIXMMU
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2021-12-04
Luke Kenneth...
enable MMU in SimRunner if requested. now HDL and...
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2021-12-04
Luke Kenneth...
test in SimState for access to RADIX memory, bypass...
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2021-12-03
Luke Kenneth...
add a namedtuple LDSTExceptionTuple which allows obtaining
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2021-12-03
Luke Kenneth...
add link to exceptions in gtkw traces
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2021-12-02
Luke Kenneth...
regspec_decode_write now stores the decoded write info...
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2021-12-02
Luke Kenneth...
specify length in RegDecodeInfo explicitly so that...
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2021-12-02
Luke Kenneth...
use namedtuple in get_rdflags
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2021-12-02
Luke Kenneth...
use namedtuple for regspec_decode
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2021-12-02
Luke Kenneth...
add module to regspec_decode_* and get_rdflags
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2021-12-02
Jacob Lifshay
move ternlogi to SHIFT_ROT unit
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2021-12-02
Jacob Lifshay
fix sv_analysis command, cuz script created by setup...
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2021-12-02
Jacob Lifshay
format code
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2021-12-01
Luke Kenneth...
fix expected state in hazard test
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2021-12-01
Luke Kenneth...
fix expected state in hazard case_regression_1
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2021-12-01
Luke Kenneth...
add a proper twin addi regression which tests Reservati...
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2021-12-01
Luke Kenneth...
add regspec_decode which takes readmode arg and returns...
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2021-11-30
Dmitry Selyutin
sv_analysis: decouple declarations and definitions
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2021-11-30
Dmitry Selyutin
sv_analysis: use is instead of eq for enums
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2021-11-30
Dmitry Selyutin
sv_analysis: fix single-line binutils comments
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2021-11-30
Luke Kenneth...
add randomised hazard test
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2021-11-30
Luke Kenneth...
add two more hazard tests
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2021-11-30
Luke Kenneth...
attempting to use PowerDecode2 in non-svp64 mode
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2021-11-27
Dmitry Selyutin
sv_analysis: decouple common disclaimer
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2021-11-27
Dmitry Selyutin
sv_analysis: introduce stub binutils format
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2021-11-27
Dmitry Selyutin
sv_analysis: support format argument
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2021-11-27
Luke Kenneth...
add extra overlap hazard test
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2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb using exts...
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2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb in alu_cases...
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2021-11-26
R Veera Kumar
Shorten expected state code for case_rand in alu_cases...
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2021-11-26
R Veera Kumar
Shorten case_rand_imm alu test case code
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2021-11-26
R Veera Kumar
Make carry_out32 variable boolean and expected state...
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2021-11-25
R Veera Kumar
Shortened code in case_addis_nonzero_r0 alu test case
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2021-11-25
R Veera Kumar
Correct add-equal operator in case_rand_imm
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2021-11-25
R Veera Kumar
Short the code of case_rand_imm
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2021-11-24
R Veera Kumar
Fix line so that 80 characters per line is kept and...
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2021-11-24
R Veera Kumar
Add expected state to case_rand_imm in alu_cases unit...
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2021-11-24
Luke Kenneth...
corrections to hazard overlap test
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2021-11-24
Luke Kenneth...
add extra hazard unit tests
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2021-11-24
Luke Kenneth...
tidyup on case_0_adde
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2021-11-24
Luke Kenneth...
correct write-after-write hazard test (expected values)
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2021-11-23
R Veera Kumar
Add expected state to case_0_adde in alu_cases unit...
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2021-11-23
Luke Kenneth...
add write-after-write hazard test for inorder core
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2021-11-23
R Veera Kumar
Add expected state to case_rand in alu_cases unit test
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2021-11-23
R Veera Kumar
Add expected state to case_addis_nonzero_r0 in alu_case...
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2021-11-23
R Veera Kumar
Add expected state to case_extsb in alu_cases unit...
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2021-11-23
R Veera Kumar
Add computed CR0 to expected version of case_adde_0
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2021-11-22
Luke Kenneth...
add expected version of case_adde_0
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2021-11-22
Luke Kenneth...
adding a couple more hazard avoidance cases
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2021-11-22
R Veera Kumar
Add expected state to case_cmpeqb in alu_cases unit...
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2021-11-22
R Veera Kumar
Add expected state to case_cmplw_microwatt_1 in alu_cas...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpli_microwatt in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0_disasm...
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2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0 in alu_case...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_4 in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_3 in alu_cases...
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2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_1 in alu_cases...
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2021-11-21
Luke Kenneth...
sigh, for overlap mode there is no safe way to get...
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2021-11-21
Luke Kenneth...
move dump state to base class State in test API
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2021-11-21
R Veera Kumar
Add expected state to case_cmp3 in alu_cases unit test
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2021-11-21
R Veera Kumar
Add expected state to case_cmp2 in alu_cases unit test
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2021-11-21
R Veera Kumar
Add expected state to case_cmp in alu_cases unit test
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2021-11-21
R Veera Kumar
Add expected state to all of case_addze in alu_cases...
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2021-11-17
Jacob Lifshay
add bitmanip_cases.py
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2021-11-17
Jacob Lifshay
rename ternary->ternlog and associated form/field TI...
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2021-11-17
Luke Kenneth...
add allow_overlap argument to TestRunnerBase
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2021-11-17
Luke Kenneth...
code-comments
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2021-11-17
Luke Kenneth...
XER regspec_decode_write was not sophisticated enough.
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2021-11-17
Luke Kenneth...
split up regression cases so that a single Rc=1 add...
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2021-11-16
Luke Kenneth...
truncate CR regspec_decode_write reg mask to 8 bit
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2021-11-16
Luke Kenneth...
argh, regspec_decode_write is supposed to return single...
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2021-11-16
Luke Kenneth...
name of cr reg3 was numbered 2
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2021-11-13
Jacob Lifshay
remove excess I from ternary-related names
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2021-11-12
Jacob Lifshay
change ternaryi to correct register fields
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2021-11-12
Jacob Lifshay
format code
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2021-11-12
Jacob Lifshay
format code
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2021-11-11
Luke Kenneth...
add case-based expected results in addme alu_cases
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2021-11-11
Luke Kenneth...
invert speedup (commenting-out) of tests
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2021-11-11
Luke Kenneth...
sort out numbering on CRs in SimState
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2021-11-11
Luke Kenneth...
whitespace
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2021-11-11
Luke Kenneth...
fix test API State.compare which was overwriting intreg...
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2021-11-11
Luke Kenneth...
https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
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2021-11-11
Luke Kenneth...
add unexpected result to see what happens
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2021-11-11
Luke Kenneth...
use append on expected state dump, not ideal but
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2021-11-11
Luke Kenneth...
add core state to gtkw
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2021-11-11
R Veera Kumar
Add expected state to case_addze for addze in alu_cases...
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2021-11-11
R Veera Kumar
Add expected state to case_1_regression for 'add' in...
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2021-11-11
R Veera Kumar
Add expected state to case_1_regression for extsb in...
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