litex.git
2012-01-21 Sebastien BourdeauducqUse meaningful class names
2012-01-20 Sebastien BourdeauducqUse new verilog.convert API
2012-01-13 Sebastien BourdeauducqWishbone: omit fixed LSBs
2012-01-13 Sebastien Bourdeauducqconvtools -> tools
2012-01-05 Sebastien BourdeauducqConvert -> convert
2011-12-18 Sebastien BourdeauducqUse new syntax
2011-12-17 Sebastien Bourdeauducquart: new design using FHDL and bank (TX only, incomplete)
2011-12-17 Sebastien Bourdeauducq32-device, 8-bit CSR bus
2011-12-17 Sebastien Bourdeauducqnorflash tb: use get_fragment
2011-12-17 Sebastien BourdeauducqMultiply system clock
2011-12-17 Sebastien Bourdeauducqclkfx module
2011-12-16 Sebastien BourdeauducqProper reset generation
2011-12-16 Sebastien BourdeauducqSupport the new FHDL syntax
2011-12-16 Sebastien BourdeauducqPay a bit more attention to PEP8
2011-12-13 Sebastien BourdeauducqInitial import