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yosys.git
2021-01-29
whitequark
Merge pull request #2564 from whitequark/flatten-improv...
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2021-01-29
Yosys Bot
Bump version
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2021-01-28
whitequark
Merge pull request #2569 from zachjs/macro-arg-surround...
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2021-01-28
Claire Xen
Merge pull request #2535 from Ravenslofty/scc-specify
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2021-01-28
Zachary Snow
verilog: strip leading and trailing spaces in macro...
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2021-01-27
Yosys Bot
Bump version
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2021-01-26
Marcelina Kościelnicka
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-26
Marcelina Kościelnicka
xilinx: Add FDRSE_1, FDCPE_1.
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2021-01-26
whitequark
Merge pull request #2563 from whitequark/cxxrtl-msvc
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2021-01-26
whitequark
Merge pull request #2544 from modwizcode/fix-clock
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2021-01-26
whitequark
flatten: clarify confusing error message.
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2021-01-26
whitequark
cxxrtl: do not use `->template` for non-dependent names.
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2021-01-26
Dan Ravensloft
scc: Add -specify option to find loops in boxes
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2021-01-26
Yosys Bot
Bump version
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2021-01-25
whitequark
Merge pull request #2549 from pgadfort/support-multiple...
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2021-01-25
whitequark
Merge pull request #2550 from zachjs/macro-arg-spaces
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2021-01-25
Yosys Bot
Bump version
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2021-01-24
Claire Xen
Merge pull request #2558 from YosysHQ/dave/chandle-dpi
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2021-01-23
David Shah
dpi: Support for chandle type
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2021-01-22
Yosys Bot
Bump version
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2021-01-21
Miodrag Milanović
Merge pull request #2553 from zachjs/rand-const-modifiers
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2021-01-21
Zachary Snow
Allow combination of rand and const modifiers
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2021-01-21
Yosys Bot
Bump version
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2021-01-20
Claire Xen
Merge pull request #2552 from YosysHQ/claire/yosyshq
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2021-01-20
Claire Xenia...
Switch verific bindings from Symbiotic EDA flavored...
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2021-01-20
Miodrag Milanović
Merge pull request #2536 from TobiasFaller/master
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2021-01-20
Miodrag Milanović
Merge pull request #2551 from zachjs/wire-logic
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2021-01-20
Zachary Snow
sv: fix support wire and var data type modifiers
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2021-01-20
Zachary Snow
verilog: allow spaces in macro arguments
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2021-01-19
Yosys Bot
Bump version
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2021-01-18
Peter Gadfort
adding support for passing multiple liberty files to abc
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2021-01-18
whitequark
Merge pull request #2547 from zachjs/plugin-so-dsym
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2021-01-18
whitequark
Merge pull request #2312 from antmicro/typedef-inout
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2021-01-18
Zachary Snow
Add plugin.so.dSYM to .gitignore
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2021-01-18
Kamil Rakoczy
Add typedef input/output test
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2021-01-18
Kamil Rakoczy
Fix input/output attributes when resolving typedef...
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2021-01-18
Lukasz Dalek
Parse package user type in module port list
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2021-01-15
Iris Johnson
Improves the previous commit with a more complete cover...
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2021-01-15
Yosys Bot
Bump version
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2021-01-14
Iris Johnson
Handle sliced bits as clock inputs (fixes #2542)
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2021-01-14
Marcelina Kościelnicka
opt_share: Fix X and CO signal width for shifted $alu...
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2021-01-14
Yosys Bot
Bump version
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2021-01-13
Claire Xen
Merge pull request #2537 from pepijndevos/spice
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2021-01-13
Pepijn de Vos
add buffer option to spice backend
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2021-01-12
Tobias Faller
Fixed missing goto statement in passes/techmap/abc.cc
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2021-01-05
Yosys Bot
Bump version
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2021-01-04
whitequark
Merge pull request #2522 from tomverbeure/simlib_typos2
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2021-01-04
Tom Verbeure
Fix some trivial typos.
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2021-01-02
Yosys Bot
Bump version
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2021-01-01
whitequark
Merge pull request #2480 from YosysHQ/dave/nexus-lram
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2021-01-01
whitequark
Merge pull request #2512 from umarcor/plugin-err
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2021-01-01
whitequark
Merge pull request #2515 from umarcor/fix/ghdl
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2021-01-01
whitequark
Merge pull request #2518 from zachjs/recursion
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2021-01-01
whitequark
Merge pull request #2517 from zachjs/sv-tf-implied...
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2021-01-01
Zachary Snow
verilog: improved support for recursive functions
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2020-12-31
Zachary Snow
sv: complete support for implied task/function port...
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2020-12-30
umarcor
makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
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2020-12-30
Yosys Bot
Bump version
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2020-12-29
umarcor
plugin: enhance no-plugin error
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2020-12-29
whitequark
Merge pull request #2509 from zachjs/issue-2427
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2020-12-29
whitequark
Merge pull request #2514 from umarcor/feat/ghdl
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2020-12-29
Yosys Bot
Bump version
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2020-12-28
umarcor
makefile: add support for built-in ghdl-yosys-plugin
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2020-12-28
whitequark
Merge pull request #2511 from umarcor/feat/msys2-32
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2020-12-28
whitequark
Merge pull request #2507 from umarcor/fix/msys2
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2020-12-28
umarcor
makefile: rename msys2 to msys2-32, config PREFIX
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2020-12-28
umarcor
kernel/yosys.h: undef CONST on WIN32
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2020-12-28
Yosys Bot
Bump version
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2020-12-27
Claire Xen
Merge pull request #2510 from YosysHQ/whitequark/CODEOW...
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2020-12-27
whitequark
CODEOWNERS: add @zachjs as Verilog/AST frontend owner
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2020-12-27
Zachary Snow
Fix elaboration of whole memory words used as indices
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2020-12-27
Yosys Bot
Bump version
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2020-12-26
Miodrag Milanović
Merge pull request #2506 from zachjs/const-arg-redeclare
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2020-12-26
Zachary Snow
Fix constants bound to redeclared function args
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2020-12-24
Yosys Bot
Bump version
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2020-12-23
whitequark
Merge pull request #2502 from ldoolitt/master
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2020-12-23
whitequark
Merge pull request #2501 from zachjs/genrtlil-tern...
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2020-12-23
whitequark
Merge pull request #2476 from zachjs/const-arg-width
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2020-12-23
Larry Doolittle
passes/pmgen/pmgen.py: trivial change to remove C+...
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2020-12-23
Zachary Snow
genrtlil: fix mux2rtlil generated wire signedness
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2020-12-23
Yosys Bot
Bump version
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2020-12-23
Zachary Snow
Fix constants bound to single bit arguments (fixes...
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2020-12-22
whitequark
Merge pull request #2499 from whitequark/cxxrtl-fixes
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2020-12-22
whitequark
cxxrtl: don't crash generating debug information for...
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2020-12-22
whitequark
Merge pull request #2498 from StefanBruens/Fix_opt_lut
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2020-12-22
whitequark
Merge pull request #2497 from whitequark/cxxrtl-reflow
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2020-12-22
whitequark
cxxrtl: split processes into sync and case nodes.
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2020-12-22
whitequark
kernel: undef Tcl macros interfering with cxxrtl.
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2020-12-22
whitequark
cxxrtl: completely rewrite netlist layout code.
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2020-12-22
StefanBruens
Fix use-after-free in LUT opt pass
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2020-12-22
whitequark
Merge pull request #2479 from zachjs/const-arg-hint
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2020-12-22
whitequark
Merge pull request #2491 from zachjs/port-bind-sign
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2020-12-22
Yosys Bot
Bump version
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2020-12-21
whitequark
cxxrtl: simplify logic choosing wire type. NFCI.
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2020-12-21
whitequark
cxxrtl: clarify node use-def construction. NFCI.
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2020-12-21
whitequark
cxxrtl: fix typo.
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2020-12-21
Marcelina Kościelnicka
xilinx: Add some missing blackbox cells.
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2020-12-21
Marcelina Kościelnicka
xilinx: Regenerate cells_xtra.v using Vivado 2020.2
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2020-12-21
whitequark
Merge pull request #2496 from whitequark/cxxrtl-fixes
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2020-12-21
whitequark
cxxrtl: speed up bit repeats (sign extends, etc).
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