2019-06-13 |
Jean-François... | vendor.xilinx_spartan6: implement DDR I/O buffers and... |
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2019-06-13 |
whitequark | compat.fhdl.structure: fix Case().makedefault(). |
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2019-06-13 |
whitequark | compat.fhdl.structure: always order default case as... |
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2019-06-13 |
whitequark | hdl.ast: tighten assertion in Switch(). |
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2019-06-12 |
whitequark | Simplify code by using Signal.like(name_suffix="..... |
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2019-06-12 |
whitequark | hdl.ast: add name_suffix=".." option to Signal.like(). |
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2019-06-12 |
Jean-François... | vendor.xilinx_7series: implement DDR I/O buffers. |
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2019-06-12 |
whitequark | vendor.lattice_ice40: fix typo. |
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2019-06-12 |
whitequark | build.{dsl,res,plat}: add PinsN and DiffPairsN. |
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2019-06-11 |
whitequark | hdl.ast: implement values with custom lowering. |
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2019-06-11 |
whitequark | back.pysim: check for a clock being added twice. |
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2019-06-11 |
whitequark | back.rtlil: mask memory init values. |
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2019-06-11 |
whitequark | hdl.mem: coerce memory init values to integers. |
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2019-06-09 |
Simon Kirkby | lib.cdc: fix typo. |
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2019-06-07 |
Jean-François... | vendor.xilinx_spartan6: implement. |
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2019-06-07 |
Jean-François... | vendor.xilinx_7series: fix typos. |
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2019-06-06 |
whitequark | build.dsl: fix precondition check in Pins. |
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2019-06-06 |
Jean-François... | vendor.xilinx_7series: implement. |
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2019-06-05 |
whitequark | build.res: allow querying frequency of a previously... |
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2019-06-05 |
whitequark | build.{dsl,res,plat}: apply clock constraints to signal... |
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2019-06-05 |
whitequark | build.dsl: replace extras= with Attrs(). |
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2019-06-05 |
whitequark | Typos and style fixes. NFC. |
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.lattice_ice40: normalize device names. |
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2019-06-04 |
whitequark | hdl.ir: rephrase elaboratable warning to not look like... |
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2019-06-04 |
whitequark | compat.fhdl.module: silence "unused elaboratable" warnings. |
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2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering for TSTripl... |
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2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering. |
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2019-06-04 |
whitequark | compat.fhdl.module: implement some TODO'd deprecation... |
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2019-06-04 |
whitequark | build.run: fix product extraction to work on Windows. |
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2019-06-04 |
whitequark | build.plat: hide executed commands in quiet builds... |
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.plat: allow (easily) overriding with an empty... |
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.module: CompatModule should be elaboratable. |
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2019-06-04 |
whitequark | build.res: use ConstraintError iff a constraint invaria... |
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2019-06-04 |
whitequark | hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. |
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2019-06-04 |
whitequark | vendor.board: split off into nmigen-boards package. |
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.run: simplify using build products locally, e... |
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2019-06-04 |
whitequark | build.res: simplify emission of port constraints on... |
commit | commitdiff | tree |
2019-06-04 |
whitequark | Clean up imports. |
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2019-06-04 |
whitequark | build.run: extract from build.plat. |
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: clk16 pin does not have a... |
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: fix typo. |
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2019-06-03 |
whitequark | vendor.conn.pmod: implement. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | examples: reorganize into examples/basic and examples... |
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2019-06-03 |
whitequark | vendor.board: extract package. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.tinyfpga_bx: add connectors. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.icestick: add connectors. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.ice40_hx1k_blink_evn: add (some) connectors. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{plat,res}: add support for connectors. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.dsl: add support for connectors. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | compat.fhdl.specials: TSTriple is not an elaboratable. |
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2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential outpu... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential input... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement SDR and DDR I... |
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2019-06-03 |
whitequark | lib.io: add i_clk and o_clk to pin layout with xdr>=1. |
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2019-06-03 |
whitequark | hdl.rec: unbreak hasattr(rec, ...). |
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2019-06-03 |
whitequark | build.{dsl,plat,res}: allow dir="oe". |
commit | commitdiff | tree |
2019-06-03 |
whitequark | lib.io: allow dir="oe". |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{res,plat}: use xdr=0 as default, not xdr=1. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: allow requesting raw ports, with dir="-". |
commit | commitdiff | tree |
2019-06-03 |
whitequark | lib.io: allow Pin(xdr=0), representing a combinatorial... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: enable SystemVerilog when... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: if not specified, request resource #0. |
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: instantiate SB_IO and apply... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.ir: accept LHS signals like slices as Instance... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.dsl: allow adding submodules with computed name... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.ir: accept expanded (kind, name, value) tuples... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{res,plat}: propagate extras to pin fragment... |
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: simplify. NFC. |
commit | commitdiff | tree |
2019-06-02 |
whitequark | build.dsl: require a dict for extras instead of a strin... |
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.fpga.lattice_ice40: use .bin suffix for bitstrea... |
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.tinyfpga_{b→bx} |
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.tinyfpga_b: fix IO_STANDARD. |
commit | commitdiff | tree |
2019-06-02 |
Simon Kirkby | vendor.tinyfpga_b: implement. |
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.icestick: fix typo. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | Travis: update install script. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.ice40_hx1k_blink_evn: implement. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.icestick: implement. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.fpga.lattice_ice40: implement. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.plat: implement. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.res: always return a Pin record. |
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.res: accept a list of clocks in ConstraintManager... |
commit | commitdiff | tree |
2019-05-26 |
whitequark | back.rtlil: allow specifying platform for convert(). |
commit | commitdiff | tree |
2019-05-26 |
whitequark | Add versioneer. |
commit | commitdiff | tree |
2019-05-26 |
whitequark | hdl.ir: silence unused elaboratable warning on interpre... |
commit | commitdiff | tree |
2019-05-26 |
Jean-François... | build.res: add ConstraintManager. |
commit | commitdiff | tree |
2019-05-25 |
whitequark | build.dsl: make Pins and DiffPairs iterable. |
commit | commitdiff | tree |
2019-05-25 |
whitequark | build.dsl: improve repr of Pins() and DiffPairs(). |
commit | commitdiff | tree |
2019-05-25 |
whitequark | hdl.rec: allow providing fields during construction. |
commit | commitdiff | tree |
2019-05-25 |
whitequark | Consider Instances a part of containing fragment for... |
commit | commitdiff | tree |
2019-05-20 |
Chris Osterwood | Add import so that Tristate.elaborate builds |
commit | commitdiff | tree |
2019-05-15 |
whitequark | hdl.ir: when adding sync domain to a design, also add... |
commit | commitdiff | tree |
2019-05-13 |
whitequark | hdl.ir: during port propagation, defs should take prior... |
commit | commitdiff | tree |
2019-05-13 |
whitequark | back.rtlil: assign undriven signals to their reset... |
commit | commitdiff | tree |
2019-05-12 |
whitequark | hdl: make all public Value classes other than Record... |
commit | commitdiff | tree |
2019-05-12 |
whitequark | hdl.ir: only pull explicitly specified ports to topleve... |
commit | commitdiff | tree |
2019-04-24 |
Jean-François... | lib.io: add a name argument to the Pin constructor. |
commit | commitdiff | tree |
2019-04-24 |
whitequark | build.dsl: style. NFC. |
commit | commitdiff | tree |
2019-04-24 |
Jean-François... | build: add DSL for defining platform resources. |
commit | commitdiff | tree |
2019-04-22 |
whitequark | back.verilog: allow stripping the src attribute, for... |
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