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riscv-tests.git
2018-10-26 Luke Kenneth... put in stuff that should not be overwritten commit | commitdiff | tree
2018-10-26 Luke Kenneth... correct addw elwidth test commit | commitdiff | tree
2018-10-26 Luke Kenneth... sv addw variable elwidth unit test commit | commitdiff | tree
2018-10-26 Luke Kenneth... sort out registers and add extra unit tests for add... commit | commitdiff | tree
2018-10-26 Luke Kenneth... add sv_add_elwidth unit test commit | commitdiff | tree
2018-10-16 Luke Kenneth... modified VL and MVL CSRs to range from 1-XLEN rather... commit | commitdiff | tree
2018-10-09 Luke Kenneth... add sv vectorised predicated beq test commit | commitdiff | tree
2018-10-09 Luke Kenneth... alter unit tests to match change in CSR table format commit | commitdiff | tree
2018-10-07 Luke Kenneth... add cleanup and comments to sv lwsp pred test commit | commitdiff | tree
2018-10-07 Luke Kenneth... add predicated version of c.lwsp sv unit test commit | commitdiff | tree
2018-10-07 Luke Kenneth... add 3rd register to c.swsp commit | commitdiff | tree
2018-10-07 Luke Kenneth... add 3 registers to sv c.lwsp commit | commitdiff | tree
2018-10-07 Luke Kenneth... add s.swsp sv test commit | commitdiff | tree
2018-10-06 Luke Kenneth... add sv c_lwsp unit test commit | commitdiff | tree
2018-10-05 Luke Kenneth... whoops overwrote x2 commit | commitdiff | tree
2018-10-04 Luke Kenneth... add twin-predicated sv c_mv unit test (no zeroing) commit | commitdiff | tree
2018-10-04 Luke Kenneth... add sv c.mv twin-predication unit test commit | commitdiff | tree
2018-10-02 Luke Kenneth... actually sv vector-vector add worked fine commit | commitdiff | tree
2018-10-02 Luke Kenneth... add rv64ud sv fadd test, shows flaw in loop for 3-arg... commit | commitdiff | tree
2018-10-01 Luke Kenneth... add vector-vector sv add commit | commitdiff | tree
2018-10-01 Luke Kenneth... add sv addi predicated unit test, including inversion... commit | commitdiff | tree
2018-10-01 Luke Kenneth... add extra sv test comments commit | commitdiff | tree
2018-10-01 Luke Kenneth... update sv test comments commit | commitdiff | tree
2018-10-01 Luke Kenneth... add sv scalar src test which highlighted flaw in spike-sv commit | commitdiff | tree
2018-10-01 Luke Kenneth... add redirection sv unit test commit | commitdiff | tree
2018-10-01 Luke Kenneth... augment sv_addi test using macros commit | commitdiff | tree
2018-10-01 Luke Kenneth... add first unit test for simple-v commit | commitdiff | tree
2018-09-24 Andrew Watermanbump env master commit | commitdiff | tree
2018-09-13 Tim NewsomeAssert if HiFive1 program is too large. commit | commitdiff | tree
2018-09-13 Tim NewsomePut debug test stack in data instead of text commit | commitdiff | tree
2018-09-08 Andrew WatermanMerge branch 'tommythorn-master' commit | commitdiff | tree
2018-09-08 Tommy ThornRV64 s{ll,ra,rl}w tests with non-canonical values commit | commitdiff | tree
2018-09-07 Andrew WatermanRevert "breakpoint.S: Don't assume trigger is hardwired... commit | commitdiff | tree
2018-09-06 Tommy Thornbreakpoint.S: Don't assume trigger is hardwired to... commit | commitdiff | tree
2018-09-03 Tim NewsomeMerge pull request #156 from riscv/PrivChange commit | commitdiff | tree
2018-08-31 Tim NewsomeFix CustomRegisterTest. commit | commitdiff | tree
2018-08-29 Tim NewsomeAdd test case for `riscv expose_custom`. commit | commitdiff | tree
2018-08-28 Tim NewsomeReset address translation/perms before PrivChange commit | commitdiff | tree
2018-08-28 Tim NewsomeNeuter TriggerStoreAddressInstant commit | commitdiff | tree
2018-08-27 Tim NewsomeMake pylint happy. commit | commitdiff | tree
2018-08-25 Andrew WatermanTemporarily disabling PrivChange test commit | commitdiff | tree
2018-08-24 Tim NewsomeMake pylint happy with change d1d2d953b5016b465. commit | commitdiff | tree
2018-08-24 Tim NewsomeGet all of the log into the final log file commit | commitdiff | tree
2018-08-23 Tim NewsomeMerge pull request #153 from dmitryryzhov/rtos-switch... commit | commitdiff | tree
2018-08-22 Tim NewsomeMerge branch 'master' of https://github.com/riscv/riscv... commit | commitdiff | tree
2018-08-22 Tim NewsomeDisable MulticoreRunHaltStepiTest commit | commitdiff | tree
2018-08-22 Dmitry RyzhovAdd debug test, which checks that openocd correctly... commit | commitdiff | tree
2018-08-21 Srivatsa YogendraChanging the register mstatus is read into (#152) commit | commitdiff | tree
2018-08-21 Andrew WatermanRevert "Fix to solve the failing tests shamt, csr and... commit | commitdiff | tree
2018-08-18 Srivatsa YogendraFix to solve the failing tests shamt, csr and scall... commit | commitdiff | tree
2018-08-17 Srivatsa Yogendramaking mtvec_handler global (#150) commit | commitdiff | tree
2018-08-13 Tim NewsomeAdd jump/hbreak test. commit | commitdiff | tree
2018-07-09 Andrew WatermanCheck that SC yields the load reservation commit | commitdiff | tree
2018-07-03 Tim Newsomerwatch/watch on explicit address commit | commitdiff | tree
2018-06-18 Tim NewsomeAdd reproduce line to the end of debug test logs commit | commitdiff | tree
2018-05-21 Tim NewsomeMerge pull request #141 from riscv/mrhstest commit | commitdiff | tree
2018-05-19 Tim NewsomeFix MulticoreRunHaltStepiTest commit | commitdiff | tree
2018-05-15 Megan WachsMerge pull request #139 from riscv/debug-tests-more... commit | commitdiff | tree
2018-05-14 Megan WachsMerge remote-tracking branch 'origin/downloadtest'... commit | commitdiff | tree
2018-05-14 Tim NewsomeMake DownloadTest properly park other harts. commit | commitdiff | tree
2018-05-14 Megan Wachsdebug: remove some unintentionally added newlines commit | commitdiff | tree
2018-05-14 Megan Wachsdebug: Fixing the non-RTOS behavior for DownloadTest commit | commitdiff | tree
2018-05-11 Megan Wachsdebug: mark more tests as single-hart tests commit | commitdiff | tree
2018-05-11 Megan Wachsdebug: output some more useful info into the post-morte... commit | commitdiff | tree
2018-05-01 Christopher... [rv64ua/lrsc] Initialize memory read out. (#135) commit | commitdiff | tree
2018-04-30 Tim NewsomeFix formatting to make pylint happy. commit | commitdiff | tree
2018-04-29 Megan WachsMerge pull request #132 from riscv/debug-clear-satp commit | commitdiff | tree
2018-04-27 Megan Wachsdebug: need to clear satp before changing priv commit | commitdiff | tree
2018-04-27 Megan WachsMerge pull request #125 from riscv/debug-delete-sim commit | commitdiff | tree
2018-04-27 Megan WachsMerge pull request #130 from riscv/trap_entry_align-1 commit | commitdiff | tree
2018-04-27 Megan Wachsdebug: add missing align directive on trap_entry commit | commitdiff | tree
2018-04-24 Tim NewsomeFix race when making logs directory commit | commitdiff | tree
2018-04-19 Megan WachsDelete E300Sim.py commit | commitdiff | tree
2018-04-16 Tim NewsomeMerge pull request #123 from riscv/gdb_timeout commit | commitdiff | tree
2018-04-09 Tim NewsomeCompute gdb command timeout based on ops estimate commit | commitdiff | tree
2018-04-09 Andrei TatarnikovFix #120: Instructions 'sll' are replaced with 'slli... commit | commitdiff | tree
2018-04-02 Tim NewsomeUse `gdb_report_register_access_error enable` commit | commitdiff | tree
2018-03-27 Tim NewsomeTest debug authentication. commit | commitdiff | tree
2018-03-23 Tim NewsomePrint log filename at the end of the log. commit | commitdiff | tree
2018-03-21 Andrew WatermanMake misa.C test conform to Hauser proposal commit | commitdiff | tree
2018-03-21 Palmer DabbeltMerge pull request #119 from rishikhan/master commit | commitdiff | tree
2018-03-19 rishiUpdate Makefile to allow for RISCV_PREFIX to be set... commit | commitdiff | tree
2018-03-01 Tim NewsomeTest debugging with/without a program buffer commit | commitdiff | tree
2018-03-01 Tim NewsomeEnsure an error when reading a non-existent CSR. commit | commitdiff | tree
2018-02-27 Andrew WatermanAdd test for clearing misa.C while PC is misaligned... commit | commitdiff | tree
2018-02-09 Tim NewsomeTest resuming from a trigger. commit | commitdiff | tree
2018-02-07 Tim NewsomeLink scripts shouldn't be executable. commit | commitdiff | tree
2018-01-08 Tim NewsomeDeal with gdb reporting pmpcfg0 not existing. commit | commitdiff | tree
2018-01-05 Tim NewsomeAdd test for multicore failure commit | commitdiff | tree
2018-01-03 Andrew WatermanTest access exception behavior for illegal addresses... commit | commitdiff | tree
2017-12-27 Tim NewsomeTest FPRs that aren't XLEN in size. commit | commitdiff | tree
2017-12-22 Tim NewsomeAdd all-tests target. commit | commitdiff | tree
2017-12-21 Megan WachsMerge pull request #110 from riscv/bump_env commit | commitdiff | tree
2017-12-21 Megan Wachstests: bump env to pick up new names for CSRs commit | commitdiff | tree
2017-12-20 Tim NewsomeRemove `set arch riscv:rv%d` commit | commitdiff | tree
2017-12-20 Tim NewsomeVerify that F18 does not exist on FPU-less targets commit | commitdiff | tree
2017-12-12 Tim NewsomeDisplay env variables used when invoking OpenOCD commit | commitdiff | tree
2017-12-01 Tim NewsomeEnsure there are no unnamed registers. commit | commitdiff | tree
2017-11-30 Tim NewsomeMerge pull request #109 from riscv/vcssim commit | commitdiff | tree
2017-11-30 Tim NewsomeClean up VcsSim init() commit | commitdiff | tree
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