git.libre-soc.org Git - yosys.git/shortlog

2013-12-01	Clifford Wolf	Progress on AppNote 011	commit \| commitdiff \| tree
2013-11-29	Clifford Wolf	Progress on AppNote 011	commit \| commitdiff \| tree
2013-11-29	Clifford Wolf	Progress on AppNote 011	commit \| commitdiff \| tree
2013-11-29	Clifford Wolf	Using RTLIL::id2cstr for prompt printing	commit \| commitdiff \| tree
2013-11-29	Clifford Wolf	Added dump -m and -n options	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Progress on AppNote 011	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Merge pull request #17 from mschmoelzer/master	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Fixed temp net name generation in rtlil process generat...	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Added pattern support to "ls" command	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Improved ID matching scheme in select (and thus for...	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Fixes and improvements in "show" command	commit \| commitdiff \| tree
2013-11-28	Martin Schmölzer	Include unistd.h in svgview.cpp (required for getcwd...	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	More progress on AppNote 011	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Added "src" attribute to processes	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Started writing appnote 011	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Added support for "show -pause" and "show -format dot"	commit \| commitdiff \| tree
2013-11-28	Clifford Wolf	Added QGraphicsWebView to yosys-svgviewer	commit \| commitdiff \| tree
2013-11-27	Clifford Wolf	Updated ABC to 9241719523f6	commit \| commitdiff \| tree
2013-11-27	Clifford Wolf	Added some svgviewer code for possible future switch...	commit \| commitdiff \| tree
2013-11-27	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	commit \| commitdiff \| tree
2013-11-27	Clifford Wolf	Tighter integration of ABC build	commit \| commitdiff \| tree
2013-11-27	Clifford Wolf	Set version number to 0.1.0+	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Started implementing undef support in "sat" command	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Bugfixes in new "stat" command	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Added "stat" command	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Improvements in satgen undef handling	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Improvements in satgen undef handling	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Added ezsat vec_const() api	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Started implementing undef handling in satgen	commit \| commitdiff \| tree
2013-11-25	Clifford Wolf	Removed undef feature from ezsat api	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Using simplemap mappers from techmap	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added simplemap pass	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added module->avail_parameters (for advanced techmap...	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added techmap -D and -I options	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added verilog frontend -ignore_redef option	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added "techmap -share_map" option	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Early wire/reg/parameter width calculation in ast/simplify	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Updated TODOs	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Fixed xilinx/example_sim_counter test bench	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added proper dumping of signed/unsigned parameters...	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added support for signed parameters in ilang	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Removed now obsolete test cases	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Remove auto_wire framework (smarter than the verilog...	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Implemented correct handling of signed module parameters	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added modelsim support to autotest	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Fixed "flatten" top-module detection: Only use on fully...	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Fixed "make install" dependencies	commit \| commitdiff \| tree
2013-11-24	Clifford Wolf	Added "top" attribute to mark top module in hierarchy	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	Updated command-reference-manual.tex	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	AppNote 010 typo fixes and corrections	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	AppNote 010 progress	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	Improved handling of techmap special wires	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	Improved handling of initialized registers	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	Added more generic _TECHMAP_ wire mechanism to techmap...	commit \| commitdiff \| tree
2013-11-23	Clifford Wolf	Making prograss on Appnote 010	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Progress on AppNote 010	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Started to write on AppNote 010: Verilog to BLIF	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Updated command-reference-manual.tex	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Renamed "placeholder" to "blackbox"	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Some driver changes/fixes	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Fixed O(n^2) performance bug in verilog preprocessor	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Added more performance measurement infrastructure	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Enable {* .. *} feature per default (removes dependency...	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Massive performance improvement from refactoring RTLIL...	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Added SigBit struct and refactored RTLIL::SigSpec:...	commit \| commitdiff \| tree
2013-11-22	Clifford Wolf	Improved make rules for profiling and debugging	commit \| commitdiff \| tree
2013-11-21	Clifford Wolf	Updated abc	commit \| commitdiff \| tree
2013-11-21	Clifford Wolf	Implemented $_DFFSR_ expression generator in verilog...	commit \| commitdiff \| tree
2013-11-21	Clifford Wolf	Fixed async proc detection in mem2reg	commit \| commitdiff \| tree
2013-11-21	Clifford Wolf	Major improvements in mem2reg and added "init" sync...	commit \| commitdiff \| tree
2013-11-21	Clifford Wolf	Fixed a bug in "add -global_input"	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Added "proc_arst -global_arst" feature	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Fixed ilang parser: memory width	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Added "add" command (only wires for now)	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Another name resolution bugfix for generate blocks	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Implemented indexed part selects	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Do not allow memory bit select on the left side of...	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Added "synthesis" in (synopsys\|synthesis) comment support	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Fixed name resolution of local tasks and functions...	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Implemented part/bit select on memory read	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Updated TODOs in README file	commit \| commitdiff \| tree
2013-11-20	Clifford Wolf	Added init= attribute for fpga-style reset values	commit \| commitdiff \| tree
2013-11-19	Clifford Wolf	Added "make config-sudo"	commit \| commitdiff \| tree
2013-11-19	Clifford Wolf	Install simlib in datdir	commit \| commitdiff \| tree
2013-11-19	Clifford Wolf	Large improvements in yosys-config	commit \| commitdiff \| tree
2013-11-19	Clifford Wolf	Fixed parsing of module arguments when one type is...	commit \| commitdiff \| tree
2013-11-19	Clifford Wolf	Renamed temp module generated by "abc" pass from "logic...	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Added additional mem2reg testcase	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Fixed two bugs in mem2reg functionality in AST frontend	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Added dumping of attributes in AST frontend	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Fixed parsing of default cases when not last case	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Fixed mem2reg for reg usage outside always block	commit \| commitdiff \| tree
2013-11-18	Clifford Wolf	Added commented-out osu025 maping commands to cmos...	commit \| commitdiff \| tree
2013-11-17	Clifford Wolf	Added -v<level> option and some minor driver cleanups	commit \| commitdiff \| tree
2013-11-16	Clifford Wolf	Renamed ABCHGPULL to ABCPULL in Makefile	commit \| commitdiff \| tree
2013-11-13	Clifford Wolf	Improved building of yosys-abc	commit \| commitdiff \| tree
2013-11-13	Clifford Wolf	Fixed abc pass blif parser for constant bits	commit \| commitdiff \| tree
2013-11-13	Clifford Wolf	Fixed parsing of "parameter integer"	commit \| commitdiff \| tree
2013-11-10	Clifford Wolf	Cleanups and bugfixes in response to new internal cell...	commit \| commitdiff \| tree
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