yosys.git
2013-10-27 Clifford WolfAdded API and Makefile rules for share/ files
2013-10-27 Clifford WolfAdded design->full_selection() helper method
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir
2013-10-27 Clifford WolfXilinx mojo_counter example is now working
2013-10-27 Clifford WolfFixed hex string generation bug in edif backend
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 Clifford WolfImproved xilinx mojo_counter example
2013-10-26 Clifford WolfAdded support for i/o buffers to iopadmap
2013-10-26 Clifford WolfAdded another xilinx example (not funcional yet)
2013-10-24 Clifford WolfAdded support for sr flip-flops to dfflibmap
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-24 Clifford WolfFixed handling of boolean attributes (passes)
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends)
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends)
2013-10-24 Clifford WolfFixed handling of boolean attributes (kernel)
2013-10-23 Clifford WolfFixed parsing of value-less attributes in ilang
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-10-18 Clifford WolfAdded handling of multiple async paths in proc_arst
2013-10-18 Clifford WolfChanged NEW_WIRE API to return the wire, not the signal
2013-10-18 Clifford WolfAdded dffsr support to proc_dff pass
2013-10-18 Clifford WolfAdded RTLIL NEW_WIRE macro
2013-10-18 Clifford WolfBugfix in dffsr techmap rules
2013-10-18 Clifford WolfAdded techmap rules for $sr, $dffsr and $dlatch
2013-10-18 Clifford WolfAdded $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
2013-10-18 Clifford WolfAdded $sr, $dffsr and $dlatch cell types
2013-10-17 Clifford WolfImproved way of connecting ports in techmap pass
2013-10-17 Clifford WolfOnly prefer connected signals iff they have public...
2013-10-17 Clifford WolfAdded -buf, -true and -false options to blif backend
2013-10-17 Clifford WolfFixed bug in synthesis of memories that are never written
2013-10-17 Clifford WolfAvoid re-arranging signals on register outputs
2013-10-17 Clifford WolfFixed detection of major wires in opt_clean
2013-10-16 Clifford WolfAdded iopadmap pass
2013-10-16 Clifford WolfMoved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 Clifford WolfAdded map, par and bitgen to xlinx7 example
2013-10-16 Clifford WolfFixed parsing or liberty file statements such as 'clock...
2013-10-11 Clifford WolfAdded recommended apt-get commands to README
2013-10-11 Clifford WolfFixed minisat include
2013-10-03 Clifford WolfPinned ABC revision to 0f9e5488ced3
2013-09-17 Clifford WolfImprovements in EDIF backend
2013-09-15 Clifford WolfAdded additional options to BLIF backend
2013-09-15 Clifford WolfAdded BLIF backend
2013-09-15 Clifford WolfA couple of small fixes in SPICE backend
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-09-15 Clifford WolfUpdated manual
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-09-03 Clifford WolfAdded -selected option to various backends
2013-08-28 Clifford WolfEncode large (>32 bits) parameters as hex string in...
2013-08-27 Clifford WolfImproved edif backend
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes...
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files
2013-08-22 Clifford WolfMore explicit integer output in verilog backend
2013-08-22 Clifford WolfAdded correct encoding of identifiers in EDIF backend
2013-08-22 Clifford WolfAdded edif backend (still under construction)
2013-08-21 Clifford WolfMerge pull request #10 from hansiglaser/master
2013-08-21 Clifford WolfSome minor documentation fixes
2013-08-21 Johann Glaserfixed Verilog parser filename and line numbering issue...
2013-08-20 Clifford WolfMerge pull request #9 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for include directories with the new...
2013-08-20 Clifford WolfMerge pull request #8 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for notif0/notif1 primitives
2013-08-20 Clifford WolfAdded cleaning of old version_* files to version_*...
2013-08-20 Clifford WolfAdded version info to yosys command and added -V option
2013-08-20 Clifford WolfMinor fixes in abc build instructions and abc pass
2013-08-19 Clifford WolfFixed width and sign detection for ** operator
2013-08-19 Clifford WolfAdded support for bufif0/bufif1 primitives
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend)
2013-08-15 Clifford WolfImplemented same div-by-zero behavior as found in other...
2013-08-15 Clifford WolfFixed signed div/mod in const eval (rounding and stuff)
2013-08-15 Clifford WolfAdded ezsat api for creation of anonymous vectors
2013-08-15 Clifford WolfAdded sat -ignore_div_by_zero switch
2013-08-15 Clifford WolfAdded eval -brute_force_equiv_checker_x mode
2013-08-12 Clifford WolfAdded support for "2**n" shifter encoding
2013-08-11 Clifford WolfAdded SAT support for $div and $mod cells
2013-08-11 Clifford WolfAdded "clean -purge" and ";;;" support
2013-08-11 Clifford WolfAdded ";;" as shortcut for "; clean;"
2013-08-10 Clifford Wolffreduce performance fix
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-08-09 Clifford WolfAdded techmap -opt mode
2013-08-09 Clifford WolfSome fixes to improve determinism
2013-08-08 Clifford WolfSort ctrl signals in fsm_extract
2013-08-08 Clifford WolfAdded -try option to freduce pass
2013-08-08 Clifford WolfAdded "clean" command (less verbose opt_clean)
2013-08-07 Clifford WolfFixed topological ordering in freduce pass
2013-08-07 Clifford WolfImproved handling of private names in opt_clean and...
2013-08-07 Clifford WolfAdded stubnets example to manual prog chapter
2013-08-06 Clifford WolfSmall bugfixes in freduce pass
2013-08-06 Clifford WolfAdded freduce command
2013-08-06 Clifford WolfFixed SigPool::del() method
2013-08-06 Clifford WolfAdded proper deallocation of history buffer
2013-08-01 Clifford WolfUpdated TODO section in README
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load)
2013-07-25 Clifford WolfAdded "help -write-web-command-reference-manual"
2013-07-25 Clifford WolfFixed comments in manual rtlil/ilang syntax
2013-07-25 Clifford WolfAdded RTLIL and Liberty syntax highlighting to manual
2013-07-24 Clifford WolfAutomatically run "proc" on extract map files
2013-07-23 Clifford WolfAdded $lut cells and abc lut mapping support
2013-07-23 Clifford WolfFixed "make clean" for manual files
2013-07-21 Clifford WolfAdded web site link to README
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