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gem5.git
2012-03-30
Andreas Hansson
MEM: Remove legacy DRAM in preparation for memory updates
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2012-03-30
Andreas Hansson
Ruby: Remove the physMemPort and instead access memory...
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2012-03-30
William Wang
MEM: Introduce the master/slave port sub-classes in C++
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2012-03-30
Andreas Hansson
CPU: Unify initMemProxies across CPUs and simulation...
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2012-03-28
Nilay Vaish
Config: Change the way options are added
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2012-03-27
Nilay Vaish
Config: Move setWorkCountOptions() to Simulation.py
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2012-03-26
Andreas Hansson
range_map: Enable const find and iteration
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2012-03-26
Andreas Hansson
Power: Change bitfield name to avoid conflicts with...
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2012-03-23
Andreas Hansson
Ruby: Fix Set::print for 32-bit hosts
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2012-03-22
Andreas Hansson
MEM: Unify bus access methods and prepare for master...
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2012-03-22
Andreas Hansson
MEM: Split SimpleTimingPort into PacketQueue and ports
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2012-03-22
Andreas Hansson
Scons: Remove Werror=False in SConscript files
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2012-03-21
Andreas Hansson
Python: Fix a conditional expression that requires...
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2012-03-21
Ali Saidi
ARM: Update stats for IT and conditional branch changes
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2012-03-21
Nathanael Premillieu
ARM: Fix case where cond/uncond control is mis-specified
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2012-03-21
Ali Saidi
ARM: Clean up condCodes in IT blocks.
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2012-03-21
Geoffrey Blake
ARM: IT doesn't need to be serializing.
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2012-03-21
Andrew Lukefahr
O3: Fix sizing of decode to rename skid buffer.
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2012-03-21
Koan-Sin Tan
ARM: Add RTC to PBX System
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2012-03-21
Brian Grayson
O3: Fix size of skid buffer between fetch and decode...
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2012-03-21
Ali Saidi
ARM: Fix uninitialized value in ARM RTC model.
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2012-03-19
Tushar Krishna
Garnet: Stats at vnet granularity + code cleanup
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2012-03-19
Andreas Hansson
gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19
Andreas Hansson
clang: Fix recently introduced clang compilation errors
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2012-03-19
Andreas Hansson
scripts: Fix to ensure that port connection count is...
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2012-03-16
Nilay Vaish
ruby_fs.py: Add call to createInterruptController()
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2012-03-16
Nilay Vaish
FSConfig.py: fix a typo makeLinuxAlphaRubySystem
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2012-03-16
Marc Orr
build: remove implicit-cache setting of scons from...
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2012-03-11
Nilay Vaish
se.py: Changes to ruby portion due to SE/FS merge
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2012-03-11
Brian Grayson
O3: Add fatal when fetchWidth > Impl::MaxWidth.
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2012-03-09
Ali Saidi
ARM: Fix memory starting at non-zero address and exceed...
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2012-03-09
Ali Saidi
ARM: Update stats for CBNZ fix.
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2012-03-09
Brian Grayson
ARM: Fix branch prediction issue with CB(N)Z instruction
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2012-03-09
Ali Saidi
ARM: Update stats for valgrind fix and replace config...
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2012-03-09
Geoffrey Blake
O3/Ozone: Eliminate dead code counting software prefetc...
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2012-03-09
Geoffrey Blake
CheckerCPU: Make some basic regression tests for CheckerCPU
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2012-03-09
Geoffrey Blake
CheckerCPU: Add function stubs to non-ARM ISA source...
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2012-03-09
Geoffrey Blake
CheckerCPU: Make CheckerCPU runtime selectable instead...
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2012-03-09
Ali Saidi
ARM: Don't reset CPUs that are going to be switched in.
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2012-03-09
Ali Saidi
System: Move code in initState() back into constructor...
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2012-03-09
Ali Saidi
ARM: Fix valgrind reported error on O3 that was causing...
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2012-03-09
Ali Saidi
cache: Allow main memory to be at disjoint address...
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2012-03-08
Gabe Black
Fix the SPARC fs regression by adding a call to createI...
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2012-03-07
Marc Orr
build scripts: Made minor modifications to reduce build...
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2012-03-06
Andreas Hansson
Stats: Update stats for changeset 8868
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2012-03-02
Steve Reinhardt
SConstruct: rename and document AddM5Option
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2012-03-02
Steve Reinhardt
SConstruct: update comments & doc strings
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2012-03-02
Steve Reinhardt
DynInst: get rid of dead MyHash code.
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2012-03-02
Andreas Hansson
CPU: Check that the interrupt controller is created...
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2012-03-02
Andreas Hansson
Stats: Fix the realview regression stats after nvmem...
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2012-03-02
Andreas Hansson
Ruby: Rename RubyPort::sendTiming to avoid overriding...
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2012-03-02
Ali Saidi
ARM: FIx a bug preventing multiple cores booting a...
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2012-03-02
Ali Saidi
ARM: FIx missing cf controller connection.
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2012-03-01
Chander Sudanthi
VNC: spacing
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2012-03-01
Ali Saidi
ARM: Add support for Versatile Express extended memory map
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2012-03-01
Ali Saidi
ARM: Add RTC device for ARM platforms.
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2012-03-01
Matt Horsnell
ARM: Add limited CP14 support.
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2012-03-01
Ali Saidi
Cache: Fix an issue with LRU when bonus block is used...
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2012-03-01
Dam Sunwoo
ARM: move kernel func event to correct location.
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2012-03-01
Giacomo Gabrielli
ARM: fix bits-to-fp conversion function declarations.
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2012-03-01
Nilay Vaish
x86: Fix x86 TLB and Walker
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2012-03-01
Nilay Vaish
x86: Fix switching of CPUs
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2012-03-01
Nilay Vaish
Config: make option ruby available always
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2012-02-29
Andreas Hansson
MEM: Make all the port proxy members const
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2012-02-29
Andreas Hansson
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
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2012-02-29
Steve Reinhardt
EIO: update stats (mostly order change, some renames)
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2012-02-26
Gabe Black
Make the IO bridge accept address headed to all the...
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2012-02-26
Gabe Black
X86: Use the M5PanicFault fault in execute methods...
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2012-02-24
Andreas Hansson
MEM: Simplify cache ports preparing for master/slave...
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2012-02-24
Andreas Hansson
MEM: Prepare mport for master/slave split
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2012-02-24
Andreas Hansson
Ruby: Simplify tester ports by not using SimpleTimingPort
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2012-02-24
Andreas Hansson
MEM: Move all read/write blob functions from Port to...
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2012-02-24
Andreas Hansson
MEM: Make port proxies use references rather than pointers
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2012-02-24
Andreas Hansson
MEM: Move port creation to the memory object(s) constru...
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2012-02-24
Andreas Hansson
CPU: Round-two unifying instr/data CPU ports across...
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2012-02-24
Andreas Hansson
MEM: Fatal when no port can be found for an address
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2012-02-20
Steve Reinhardt
SimObject: make get_config_as_dict() tolerate undefined...
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2012-02-14
Andreas Hansson
MEM: Fix residual bus ports and make them master/slave
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2012-02-14
Andreas Hansson
Script: Fix the scripts that use the num_cpus cache...
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2012-02-14
Andreas Hansson
MEM: Fix master/slave ports in Ruby and non-regression...
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2012-02-13
Ali Saidi
bp: fix up stats for changes to branch predictor
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2012-02-13
Mrinmoy Ghosh
BPred: Fix RAS to handle predicated call/return instruc...
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2012-02-13
Mrinmoy Ghosh
BP: Fix several Branch Predictor issues.
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2012-02-13
Andreas Hansson
MEM: Explicit ports and Python binding on CopyEngine
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2012-02-13
Andreas Hansson
MEM: Pass the ports from Python to C++ using the Swig...
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2012-02-13
Andreas Hansson
MEM: Introduce the master/slave port roles in the Pytho...
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2012-02-13
Ali Saidi
tests: fix diff-out script for op/inst stat changes.
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2012-02-13
Gabe Black
X86: open flags: Another patch from Vince Weaver
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2012-02-12
Ali Saidi
configs: fix minor config bugs posted on the mailing...
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2012-02-12
Ali Saidi
stats: update stats for insts/ops and master id changes
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2012-02-12
Anthony Gutierrez
cpu: add separate stats for insts/ops both globally...
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2012-02-12
Dam Sunwoo
mem: fix cache stats to use request ids correctly
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2012-02-12
Ali Saidi
mem: Add a master ID to each request object.
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2012-02-12
Mrinmoy Ghosh
prefetcher: Make prefetcher a sim object instead of...
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2012-02-12
Nilay Vaish
Regressions: Update stats due to change in MESI protocol
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2012-02-11
Gabe Black
SPARC: Make PSTATE and HPSTATE a BitUnion.
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2012-02-10
Nilay Vaish
Ruby: Remove isTagPresent() calls from Sequencer.cc
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2012-02-10
Nilay Vaish
MESI: Add queues for stalled requests
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2012-02-10
Nilay Vaish
sim/system: initialize the pagePtr variable
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2012-02-10
Nilay Vaish
Regressions: Update stats due to O3 CPU changes
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