yosys.git
2017-12-14 Clifford WolfAdd RTLIL::Const::is_fully_ones()
2017-12-14 Clifford WolfAdd SigSpec::is_fully_ones()
2017-12-13 Clifford WolfMerge pull request #469 from kkiningh/master
2017-12-13 Kevin KininghamUse quote includes for yosys.h
2017-12-13 Clifford WolfCheck for memories in clk2fflogic
2017-12-13 Clifford WolfMerge pull request #468 from grahamedgecombe/fix-sb...
2017-12-12 Clifford WolfAdd warnings for driver-driver conflicts between FFs...
2017-12-10 Graham EdgecombeFix port names in SB_IO_OD
2017-12-10 Graham EdgecombeRemove trailing comma from SB_IO_OD port list
2017-12-10 Clifford WolfAdd support for Verific PRIM_SVA_NOT properties
2017-12-09 Clifford WolfAdd Verific OPER_SVA_STABLE support
2017-12-09 Clifford WolfRefactoring Verific SVA rewriter
2017-12-09 Clifford WolfMerge pull request #467 from mithro/patch-1
2017-12-09 Tim AnsellFix spelling in -vpr help for synth_ice40
2017-12-03 Clifford WolfUse "hg ... --insecure" for cloning/pulling ABC
2017-12-02 Clifford WolfUpdate ABC to hg rev 31fc97b0aeed
2017-12-02 Clifford WolfFix error handling for nested always/initial
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k
2017-11-28 David ShahAdd remaining UltraPlus cells to ice40 techlib
2017-11-27 Clifford WolfFixed "yosys-smtbmc -g" handling of no solution
2017-11-26 Clifford WolfMerge pull request #460 from mithro/g3-fixes
2017-11-26 Clifford WolfMerge pull request #461 from mithro/travis-rework
2017-11-26 Tim 'mithro... travis: Print branches before fetching, try both locations.
2017-11-26 Tim 'mithro... minisat: Make update script executable.
2017-11-26 Tim 'mithro... minisat: Only define __STDC_XXX_MACROS if not already...
2017-11-26 Tim 'mithro... minisat: Remove template with gzFile specialization.
2017-11-26 Tim 'mithro... subcircuit: Class with virtual methods should have...
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-24 Tim 'mithro... travis: Use the cache.
2017-11-24 Tim 'mithro... travis: Adding gcc-4.8 and gcc-6 on Linux.
2017-11-24 Tim 'mithro... travis: Reworking travis setup.
2017-11-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-11-23 Clifford WolfAdd Verilog "automatic" keyword (ignored in synthesis)
2017-11-18 Clifford WolfMerge pull request #455 from daveshah1/up5k
2017-11-18 David ShahRemove unnecessary keep attributes
2017-11-18 Clifford WolfAccept real-valued delay values
2017-11-18 Clifford WolfMerge pull request #452 from cr1901/master
2017-11-18 Clifford WolfMerge pull request #453 from dh73/master
2017-11-17 David ShahMerge branch 'master' into up5k
2017-11-16 Clifford WolfAdd "synth_ice40 -vpr"
2017-11-16 David ShahAdd some UltraPlus cells to ice40 techlib
2017-11-15 dh73Fixed the -vout flag to -vqm in examples/intel directory
2017-11-14 William D.... Accommodate Windows-style paths during include-file...
2017-11-09 dh73Initial Cyclone 10 support
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-11-09 dh73Organizing Speedster file names
2017-11-08 Clifford WolfAdd support for editline as replacement for readline
2017-10-31 Clifford WolfAdd "ltp" command
2017-10-29 Clifford WolfFix SMT2 handling of initstate in sub-modules
2017-10-26 Clifford WolfFix memory corruption bug in opt_rmdff
2017-10-26 Clifford WolfFix typo in opt_clean log message
2017-10-25 Clifford WolfImprove smtio performance by using reader thread, not...
2017-10-25 Clifford WolfUse separate writer thread for talking to SMT solver...
2017-10-25 Clifford WolfImprove p_* functions in smtio.py
2017-10-25 Clifford WolfDisable OSX in .travis.yml
2017-10-25 Clifford WolfAdd ENABLE_DEBUG config flag
2017-10-25 Clifford WolfUpdate ABC to hg rev f6838749f234
2017-10-25 Clifford WolfRemove vhdl2verilog
2017-10-25 Clifford WolfCapsulate smt-solver read/write in separate functions
2017-10-25 Clifford WolfFix a bug in yosys-smtbmc in ROM handling
2017-10-20 Clifford WolfRemove PSL example from tests/sva/
2017-10-20 Clifford WolfRemove all PSL support code from verific.cc
2017-10-20 Clifford WolfMerge pull request #437 from mithro/master
2017-10-20 Tim 'mithro... Adding COPYING file with license information.
2017-10-14 Clifford WolfRevert 90be0d8 as it causes endless loops for some...
2017-10-13 Clifford WolfAdd "verific -vlog-libdir"
2017-10-13 Clifford WolfAdd "verific -vlog-incdir" and "verific -vlog-define"
2017-10-13 Clifford WolfUpdate Verific README
2017-10-12 Clifford WolfMerge pull request #434 from Kmanfi/vector_fix
2017-10-12 Kaj TuomiFix input vector for reduce cells.
2017-10-12 Clifford WolfAdd Verific fairness/liveness support
2017-10-11 Clifford WolfUpdate ABC to hg rev 6283c5d99b06
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-10-10 Clifford WolfStart work on pre-processor for Verific SVA properties
2017-10-10 Clifford WolfRewrite ABC output to include proper net names in timin...
2017-10-10 Clifford WolfAdd timing constraints to osu035 example
2017-10-10 Clifford WolfRemove some dead code
2017-10-10 Clifford WolfAllow $past, $stable, $rose, $fell in $global_clock...
2017-10-07 Clifford WolfAdd $shiftx support to verilog front-end
2017-10-06 Clifford WolfUpdate ABC to hg rev 0fc1803a77c0
2017-10-05 Larry DoolittleClean whitespace and permissions in techlibs/intel
2017-10-05 Clifford WolfImprove handling of Verific errors
2017-10-04 Clifford WolfImprove Verific error handling, check VHDL static asserts
2017-10-04 Clifford WolfAdd blackbox command
2017-10-04 Clifford WolfFix nasty bug in Verific bindings
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github...
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:...
2017-10-03 Clifford WolfMerge branch 'dh73-master'
2017-10-03 Clifford WolfRename "write_verilog -nobasenradix" to "write_verilog...
2017-10-02 dh73Tested and working altsyncarm without init files
2017-10-01 dh73Fixed wrong declaration in Verilog backend
2017-10-01 dh73Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
2017-09-30 Udi FinkelsteinTurned a few member functions into const, esp. dumpAst...
2017-09-30 Udi FinkelsteinResolved classical Bison IF/THEN/ELSE shift/reduce...
2017-09-29 Clifford WolfAdd first draft of eASIC back-end
2017-09-29 Clifford WolfFix synth_ice40 doc regarding -top default
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-28 Clifford WolfMerge pull request #421 from stephengroat/osx-travis
2017-09-27 Stephendelete bad backslash
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