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yosys.git
2017-02-12
Clifford Wolf
Do not eagerly fix port widths on parameterized cells
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2017-02-12
Clifford Wolf
Add "yosys -w" for suppressing warnings
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2017-02-11
Clifford Wolf
Add support for verific mem initialization
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2017-02-11
Clifford Wolf
Fix another stupid bug in the same line
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2017-02-11
Clifford Wolf
Add verific support for initialized variables
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2017-02-11
Clifford Wolf
Improve handling of Verific warnings and error messages
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2017-02-11
Clifford Wolf
Fix extremely stupid typo
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2017-02-11
Clifford Wolf
Add log_wire() API
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2017-02-11
Clifford Wolf
Fixed some "used uninitialized" warnings in opt_expr
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2017-02-11
Clifford Wolf
Evaluate all the $(shell ...) stuff for CXXFLAGS et...
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2017-02-11
Clifford Wolf
Merge branch 'stv0g-master'
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2017-02-11
Clifford Wolf
Make MacOS Makefile stuff more compact
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-11
Clifford Wolf
Add optimization of (a && 1'b1) and (a || 1'b0)
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2017-02-11
Clifford Wolf
Merge pull request #308 from C-Elegans/opt_compare_fix_pr
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2017-02-10
C-Elegans
Fix issue #306, "Bug in opt -full"
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2017-02-10
Steffen Vogel
Use pkg-config for linking tcl-tk
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2017-02-10
Steffen Vogel
Dont mix Homebrew and MacPorts build options
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2017-02-09
Steffen Vogel
Remove space after backslash
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2017-02-09
Steffen Vogel
Applied fixes from @joshhead (thanks for your effors!)
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2017-02-09
Clifford Wolf
Fix handling of init attributes with strange width
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2017-02-09
Clifford Wolf
Add checker support to verilog front-end
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2017-02-09
Clifford Wolf
Add "rand" and "rand const" verific support
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2017-02-08
Clifford Wolf
Add SV "rand" and "const rand" support
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2017-02-08
Clifford Wolf
Add PSL parser mode to verific front-end
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2017-02-07
Steffen Vogel
Added notes for compilation on OS X
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2017-02-07
Steffen Vogel
Fix compilation on OS X in order to support both MacPor...
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2017-02-07
Steffen Vogel
Allow standard tools to be overwritten in make invocation
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2017-02-06
Clifford Wolf
Add "read_blif -wideports"
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2017-02-05
Clifford Wolf
Fix undef propagation bug in $pmux SAT model
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2017-02-05
Clifford Wolf
Update ABC to hg rev a2fcd1cc61a6
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2017-02-05
Clifford Wolf
Merge pull request #304 from esden/gsed-darwin
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2017-02-05
Piotr Esden...
Use -E sed parameter instead of -r.
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2017-02-04
Clifford Wolf
Add assert check in "yosys-smtbmc -c"
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2017-02-04
Clifford Wolf
Improve yosys-smtbmc cover() support
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2017-02-04
Clifford Wolf
Partially implement cover() support in yosys-smtbmc
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2017-02-04
Clifford Wolf
Further improve cover() support
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2017-02-04
Clifford Wolf
Add assert/assume support to verific front-end
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2017-02-01
Clifford Wolf
Update ABC to hg rev fe96921e5d50
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2017-02-01
Clifford Wolf
Update ABC scripts to use "&nf" instead of "map"
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2017-01-31
Clifford Wolf
Merge branch 'C-Elegans-opt_compare_pr'
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2017-01-31
Clifford Wolf
Fix indenting and log messages in code merged from...
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2017-01-31
Clifford Wolf
Merge branch 'opt_compare_pr' of https://github.com...
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2017-01-31
Steffen Vogel
use Homebrew only if installed
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2017-01-31
Clifford Wolf
Improve opt_rmdff support for $dlatch cells
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2017-01-30
C-Elegans
Refactor and generalize the comparision optimization
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2017-01-30
Clifford Wolf
Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename...
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2017-01-30
Clifford Wolf
Add $ff and $_FF_ support to equiv_simple
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2017-01-28
Clifford Wolf
Add "yosys-smtbmc --aig-noheader" and AIGER mem init...
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2017-01-26
Clifford Wolf
Be more conservative with merging large cells into...
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2017-01-26
Clifford Wolf
Add warnings for quickly growing FSM table size in...
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2017-01-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-01-25
Clifford Wolf
Fix RTLIL::Memory::start_offset initialization
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2017-01-21
C-Elegans
Do not use b.as_int() in calculation of bit set
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2017-01-17
Clifford Wolf
Add "enum" and "typedef" lexer support
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2017-01-16
C-Elegans
Optimize compares to powers of 2
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2017-01-16
Clifford Wolf
Merge pull request #293 from thoughtpolice/minor-cleanup
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2017-01-15
Austin Seipp
passes/hierarchy: delete some dead code
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2017-01-15
C-Elegans
Fix issue #269, optimize signed compare with 0
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2017-01-15
Clifford Wolf
Fix bug in AstNode::mem2reg_as_needed_pass2()
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2017-01-11
Clifford Wolf
Fix $initstate handling bug in yosys-smtbmc
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2017-01-11
Clifford Wolf
Update ABC to hg id f8cadfe3861f
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2017-01-08
Clifford Wolf
Updated ABC to hg id 38b26a543f1d
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2017-01-05
Clifford Wolf
Fixed handling of local memories in functions
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2017-01-04
Clifford Wolf
Added "check -initdrv"
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2017-01-04
Clifford Wolf
Added handling of local memories and error for local...
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2017-01-04
Clifford Wolf
Implicitly set "yosys-smtbmc --noprogress" on windows
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2017-01-04
Clifford Wolf
Fixed typo in tests/simple/arraycells.v
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2017-01-04
Clifford Wolf
Fixed "yosys-smtbmc --noprogress"
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2017-01-03
Clifford Wolf
Added Verilog $rtoi and $itor support
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2017-01-02
Clifford Wolf
Handle "always 1" like "always -1" in .smtc files
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2017-01-01
Clifford Wolf
Added cell port resizing to hierarchy pass
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2016-12-31
Clifford Wolf
Updated ABC to hg id 55cd83f432c0
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2016-12-31
Clifford Wolf
Bugfix in RTLIL::SigSpec::remove2()
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2016-12-29
Clifford Wolf
Updated ABC to hg id 8c6a635f7a20
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2016-12-29
Clifford Wolf
Improved write_json help message
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2016-12-26
Clifford Wolf
Updated ABC to hg id f591c081d5e7
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2016-12-24
Clifford Wolf
Merge pull request #284 from azonenberg/master
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2016-12-23
Andrew Zonenberg
Merge pull request #1 from azonenberg-hk/master
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2016-12-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-23
Clifford Wolf
Simplified log_spacer() code
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2016-12-22
Clifford Wolf
Added "yosys -W regex"
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2016-12-21
Clifford Wolf
Added AIGER back-end to automatic back-end detection
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2016-12-21
Clifford Wolf
Updated ABC to hg rev a4872e22c646
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2016-12-21
Clifford Wolf
Updated ABC to hg rev 8bab2eedbba4
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2016-12-21
Andrew Zonenberg
greenpak4: Added INT pin to GP_SPI
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2016-12-21
Andrew Zonenberg
greenpak4: removed unused MISO pin from GP_SPI
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2016-12-20
Andrew Zonenberg
greenpak4: Removed SPI_BUFFER parameter
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2016-12-20
Andrew Zonenberg
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
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2016-12-20
Andrew Zonenberg
greenpak4: Changed port names on GP_SPI for clarity
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2016-12-20
Andrew Zonenberg
greenpak4: Initial implementation of GP_SPI cell
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2016-12-17
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-17
Andrew Zonenberg
greenpak4: Updated GP_DCMP cell model
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2016-12-16
Andrew Zonenberg
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
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2016-12-15
Clifford Wolf
Added "verilog_defines" command
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2016-12-15
Andrew Zonenberg
greenpak4: Initial version of GP_DCMP skeleton (not...
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2016-12-14
Andrew Zonenberg
greenpak4: More fixups of GP_DCMPx cells
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2016-12-14
Andrew Zonenberg
greenpak4: And another typo :(
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2016-12-14
Andrew Zonenberg
greenpak4: Fixed another typo
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