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riscv-isa-sim.git
2013-07-31
Andrew Waterman
Fix dumb ERET bug
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2013-07-29
Andrew Waterman
Don't flush TLB on PTBR writes (only FATC)
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2013-07-27
Andrew Waterman
New supervisor mode
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2013-07-27
Andrew Waterman
Remove more vector stuff
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2013-07-27
Andrew Waterman
Rename MFTX/MXTF to FMV
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2013-07-26
Andrew Waterman
Rip out Hwacha for now
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2013-07-26
Andrew Waterman
Rip out RVC for now
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2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-25
Andrew Waterman
Remove JALR static hints
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2013-07-23
Andrew Waterman
Kill spike when xspike is SIGINTed
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2013-07-22
Andrew Waterman
Don't use stdout for debugging
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2013-07-22
Andrew Waterman
Add xspike program
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2013-07-20
Andrew Waterman
Use calloc to allocate target memory
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2013-07-13
Andrew Waterman
Eliminate infinite loop in debug mode
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2013-07-13
Andrew Waterman
Exit cleanly from debug console
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2013-07-13
Andrew Waterman
Favor procs.size() over num_cores()
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2013-07-13
Andrew Waterman
Fix SR_U64 bit being ignored
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2013-06-03
Andrew Waterman
make spike.o correctly depend on dispatch.h
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2013-06-03
Andrew Waterman
use coreutils `seq' instead of hacky `range'
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2013-05-15
Yunsup Lee
change riscv-isa-run to spike in documentation
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2013-05-15
Yunsup Lee
fix make issue
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2013-05-14
Yunsup Lee
change riscv-isa-run to spike
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2013-05-06
Andrew Waterman
make Makefile sh-friendly
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2013-04-25
Andrew Waterman
use inttypes macros to print uint64_t
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2013-04-25
Andrew Waterman
fix(?) circular dependence on generated headers
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2013-04-25
Andrew Waterman
add range(start, end) method to Makefile
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2013-04-24
Yunsup Lee
fixes to correctly simulate the vector unit
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2013-04-23
Andrew Waterman
make interactive mode cope with canonical terminal
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2013-04-23
Andrew Waterman
destroy htif on simulator termination
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2013-04-22
Andrew Waterman
correctly depend on dispatch.h
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2013-04-20
Andrew Waterman
remove circular dependence in Makefile
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2013-04-20
Andrew Waterman
update abi register names
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2013-04-17
Andrew Waterman
add AUIPC insn; remove RDNPC insn
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2013-03-30
Andrew Waterman
add load-reserved/store-conditional instructions
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2013-03-30
Andrew Waterman
ignore writes to SR IP field
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2013-03-27
Andrew Waterman
opcodes.h must only contain DECLARE_INSN() lines
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2013-03-26
Andrew Waterman
add BSD license
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2013-03-26
Andrew Waterman
update ancient README
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2013-03-26
Andrew Waterman
truncate effective addresses in rv32
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2013-03-26
Andrew Waterman
expose pending interrupts in status register
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2013-03-26
Andrew Waterman
add missing #include
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2013-03-26
Andrew Waterman
ignore host writes to fromhost if old value not 0
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2013-03-26
Andrew Waterman
support compilation with gcc 4.7
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2013-02-15
Andrew Waterman
fix D$ model not acknowledging stores
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2013-02-15
Andrew Waterman
specialize fully-associative caches
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2013-02-15
Andrew Waterman
don't store host pointers in soft TLB
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2013-02-13
Andrew Waterman
clean up fetch-execute loop a bit
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2013-02-13
Andrew Waterman
add I$/D$/L2$ simulators
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2013-02-13
Andrew Waterman
migrate to c++11
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2013-02-13
Andrew Waterman
make HTIF interactions deterministic; fix race
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2013-01-26
Andrew Waterman
remove unnecessary #include
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2013-01-26
Andrew Waterman
change htif to link against libfesvr
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2012-11-13
Yunsup Lee
fix vector code simulation problem, turn on SR_U64
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2012-08-31
Andrew Waterman
new tohost/fromhost semantics
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2012-08-02
Andrew Waterman
new tohost/fromhost semantics
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2012-07-23
Andrew Waterman
correct HTIF reset behavior
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2012-05-16
Andrew Waterman
fix htif interaction with interactive mode
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2012-05-09
Andrew Waterman
per-core tohost/fromhost registers
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2012-03-24
Andrew Waterman
new supervisor mode
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2012-03-24
Yunsup Lee
add disasm functions for vector
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2012-03-20
Andrew Waterman
make NaN behavior consistent with hardfloat
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2012-03-20
Andrew Waterman
fix double-precision NaNs
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2012-03-20
Andrew Waterman
abstract regfile write port
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2012-03-20
Andrew Waterman
abstract regfile behind object
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2012-03-19
Andrew Waterman
update vector fences
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2012-03-18
Yunsup Lee
clean up vector exception instructions
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2012-03-14
Yunsup Lee
add more instructions for vector exception handling
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2012-03-14
Yunsup Lee
add vvcfg,vtcfg
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2012-03-13
Yunsup Lee
opcodes cleanup
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2012-03-13
Andrew Waterman
always propagate default NaN (all bits set)
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2012-03-10
Yunsup Lee
slight change to vector supervisor instructions
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2012-03-03
Yunsup Lee
add place holders for instructions to handle vector...
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2012-03-03
Yunsup Lee
new instructions to handle vector exceptions
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2012-02-20
Andrew Waterman
new HTIF protocol. update your fesvr.
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2012-02-20
Andrew Waterman
fixed a bug in remu[w]
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2012-02-18
Andrew Waterman
implement lighter-weight htif packet header
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2012-02-16
Andrew Waterman
reimplement div[u][w]/rem[u][w]
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2012-02-13
Andrew Waterman
fix sltu disassembly
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2012-02-09
Yunsup Lee
initialize tohost and fromhost
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2012-02-01
Andrew Waterman
remove debug printf
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2012-02-01
Andrew Waterman
poll HTIF occasionally
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2012-01-31
Andrew Waterman
don't set badvaddr for instruction access faults
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2012-01-30
Yunsup Lee
fix divide by zero bugs
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2012-01-24
Andrew Waterman
check that virtual addresses are sign-extended
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2012-01-23
Andrew Waterman
disentangle decode.h from other headers
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2012-01-23
Andrew Waterman
work around gcc 4.4 bug
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2012-01-12
Andrew Waterman
fix compilation for gcc 4.6.1
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2011-12-11
Yunsup Lee
fix utidx assign bug, make ut code execute faster
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2011-12-11
Yunsup Lee
fix the fpr abi names
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2011-11-12
Your Name
Remove dependence on binutils
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2011-11-11
Andrew Waterman
Use new compiler toolchain's disassembler
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2011-11-11
Andrew Waterman
Changed MFTX to use rs1 for its source
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2011-11-11
Andrew Waterman
Changed supervisor mode
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2011-11-01
Andrew Waterman
Fixed tight coupling of host and target page size
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2011-10-27
Andrew Waterman
changed page size to 8KB
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2011-10-19
Yunsup Lee
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim
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2011-10-19
Yunsup Lee
fix vf
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2011-10-19
Yunsup Lee
yunsup made this fix..ask him
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2011-08-18
Andrew Waterman
don't forget to commit configure after autoconf!
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2011-07-13
Rimas Avizienis
added #include <stdlib.h> to get rid of errors building...
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