gem5.git
2019-12-10 Adrian Herreradev-arm: GenericTimer, freq as 32-bit value
2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
2019-12-09 Rahul Thakurtests: Increase jenkins test timeout to 4 hours.
2019-12-08 Alec Roelkearch-riscv: set MaxMiscDestRegs to 2
2019-12-07 Gabe Blackscons: Set the partial linking group for EXTRAS dirs.
2019-12-07 Gabe Blackscons: Fixes to improve python 3 support.
2019-12-06 Daniel R. Carvalhoutil: Add a git commit-msg hook
2019-12-06 Gabe Blackkvm,arm: Update the KVM ARM v8 CPU to use vector regs.
2019-12-06 Xin Ouyangarch-riscv: fix asmtest concurrent issues.
2019-12-05 Andrea Mondelliarch-x86: missing override specifier
2019-12-05 marjanfariborzarch-x86: Adding LDDQU instruction
2019-12-04 Gabe Blacksim: Add a suppression mechanism to the SyscallReturn...
2019-12-04 Gabe Blacksim: Small style fixes in sim/syscall_return.hh.
2019-12-04 Gabe Blacksim: Change the syscall executor to a std::function.
2019-12-04 Gabe Blacksparc: Fix the getresuidFunc prototype.
2019-12-04 Gabe Blacksparc: Fix the predecoder's moreBytes method.
2019-12-03 Gabe Blacksystemc: Purposefully *expose* bind in the initiator...
2019-12-03 Gabe Blackfastmodel: Switch the diagnostic pragmas to GCC from...
2019-12-03 Bobby R. Brucemisc: CONTRIBUTING.md to advise linking Jira Issues...
2019-12-03 Brandon Pottercpu,sim-se: move error checks in syscall methods
2019-12-03 Gabe Blacksystemc,fastmodel: Use the gem5_scons error and warning...
2019-12-03 Gabe Blacksystemc: Suppress a spurious clang warning in the syste...
2019-12-03 Gabe Blacksystemc: Fix up some lingering Accellera specific code...
2019-12-03 Ciro Santillibase: add the FmtStackTrace debug option
2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implemen...
2019-12-03 Gabe Blacksystemc: Add a bunch of missing overrides to the system...
2019-12-03 Gabe Blackfastmodel: Suppress a spurious warning on clang for...
2019-12-01 Ian Jiangarch-riscv: Fix disassembling of immediate for c.lui...
2019-11-28 Ciro Santillidev-arm: Automatically assign PCI device ids in attachP...
2019-11-28 Adrian Herreradev-arm: device name in AmbaFake accesses
2019-11-28 Gabe Blackmem-cache: Avoid hiding a virtual method in the diction...
2019-11-28 Gabe Blackmem-cache: Remove a std::move clang says is unnecessary.
2019-11-28 Gabe Blackarm: Make sure not to shift off of the end of a uint32_...
2019-11-27 Giacomo Travaglinibase, python: Allow dirname selection for the interpreter
2019-11-27 Giacomo Travagliniconfigs: Add --redirects for syscall emulation
2019-11-27 Giacomo Travaglinibase: Fix DPRINTF_UNCONDITIONAL on gem5.fast
2019-11-27 Giacomo Travagliniconfigs: Add root redirect path in SE mode only when set
2019-11-27 Giacomo Travaglinisim-se: Check Path redirection when mmapping
2019-11-27 Giacomo Travagliniconfigs: Fix baremetal platform
2019-11-26 Ciro Santillisim: prefix --debug-flags Event logs with the flag...
2019-11-26 Ciro Santillicpu: prefix ExecEnable to the native trace to match...
2019-11-26 Ciro Santillibase: generalize ExecTicks to all messages with FmtTicksOff
2019-11-26 Ciro Santillibase: create DPRINTF_UNCONDITIONAL
2019-11-26 Ciro Santillibase: add the --debug-flag to DPRINTF output with FmtFlag
2019-11-26 Giacomo Travagliniarch-arm: Make the Tarmac parsed registers case insensitive
2019-11-26 Ian Jiangarch-riscv: Fix immediate decoding for integer shift...
2019-11-26 Ian Jiangarch-riscv: Fix disassembling for fence and fence.i
2019-11-26 Gabe Blackarch,cpu: Get rid of ISA_HAS_CC_REGS and its associated...
2019-11-25 Gabe Blackarm: Stop serializing ISA values wihch are cached from...
2019-11-25 Adrian Herreraarch-arm: default MIDR for Armv8 ISA processors
2019-11-25 Giacomo Travaglinidev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
2019-11-25 Ciro Santillicpu: log thread activate and suspend with --debug-flags...
2019-11-25 Ciro Santillisim-se: don't wake up threads that are halted on futex
2019-11-25 Ian Jiangarch-riscv: Fix disassembling for atomic instructions
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of operand list for compr...
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of immediate for U-type...
2019-11-22 IanJiangICTarch-riscv: Fix bug in serialize and unserialize of...
2019-11-21 Gabe Blackscons: Use the new error() and warning() methods.
2019-11-21 Gabe Blackscons: Add "warning" and "error" methods.
2019-11-21 Gabe Blackscons: Use HAVE_PROTOC when building protobuf files.
2019-11-21 Gabe Blackscons: Don't use PROTOC for the protoc command and...
2019-11-21 Bobby R. Brucetests,base: Added GTests for exec_ecoff.h and exec_aout.h
2019-11-21 Bobby R. Brucetest,base: Added GTest for base/loader/image_file_data.cc
2019-11-21 Giacomo Travaglinibase: Remove tests making use of Big/LittleEndianOrder...
2019-11-20 Brandon Potterbase,tests: Expanded GTests for addr_range.hh
2019-11-20 Ciro Santillisystem-arm: gitignore the aarch64 bootloader object...
2019-11-20 Ciro Santillisystem-arm: ignore .gen directory that contains DTS...
2019-11-20 Bertrand Marquissystem-arm: Use dts include instead of cpp in ARM DTBs
2019-11-20 Bertrand Marquissystem-arm: Rework boot loader makefile to be more...
2019-11-20 Bobby R. Brucetests, base: Added GTests for base/intmath.cc
2019-11-20 Mahyar Samanitests, base: Removed dead code from base/intmath
2019-11-18 Gabe Blackarch: Get rid of the (Big|Little)EndianGuest namespaces.
2019-11-18 Gabe Blackarch: Make and use endian specific versions of the...
2019-11-18 Adrian Herreraarch-arm: R/W interface to AArch32 HCR2 misc reg
2019-11-18 Isaac Sánchez... mem-cache: Initialize all members of `QueuedPrefetcher...
2019-11-18 Isaac Sánchez... mem-cache: Fix destructor of `BasePrefetcher::PrefetchI...
2019-11-18 Giacomo Travagliniarch-arm: Fix short descriptors cacheability during...
2019-11-18 Giacomo Travagliniarch-arm: Fix long descriptors cacheability during...
2019-11-16 Bobby R. Brucetests: Added GTests for byteswap.hh
2019-11-14 Giacomo Travaglinitests: Specify a non-default root folder for regressions
2019-11-14 Mahyar Samanitests, base: Removed ambiguity from base/intmath.hh
2019-11-14 Chun-Chen TK Hsuarch-arm: Refactor code to check if gic is GicV2
2019-11-14 Chun-Chen TK Hsuconfig: Add fastmodel cluster in fs_bigLITTLE.py
2019-11-14 Chun-Chen TK Hsufastmodel: Add VExpressFastmodel platform
2019-11-13 Gabe Blackarm: Replace most htog and gtoh with htole and letoh.
2019-11-13 Adrian Herreraarch-arm: fix routeToHyp for AArch64 in faults
2019-11-13 Bobby R. Brucetests: Added GTests for base/chunk_generator.hh
2019-11-13 Gabe Blackfastmodel: Implement reading vector registers with...
2019-11-13 Bobby R. Brucetests: Added GTests for base/types.cc
2019-11-12 Bobby R. Brucetests,base: Added GTests for base/condcodes.hh
2019-11-12 Giacomo Travaglinitests: Using super in arm_generic whenever possible
2019-11-12 Giacomo Travaglinitests: Using super for calling superclass __init__
2019-11-12 Giacomo Travaglinitests: Remove Noncoherent cache from regressions
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