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yosys.git
2015-05-03
eddiehung
Fix for all zero mask
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2015-05-03
eddiehung
Escape '<' and '>' some more
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2015-04-28
eddiehung
For vtr, escape angle brackets as well
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2015-04-28
eddiehung
blifwriter: write out .names for true/false/undef type...
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2015-02-09
Clifford Wolf
Yosys 0.5
yosys-0.5
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2015-02-09
Clifford Wolf
Bugfix in "make vcxsrc"
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2015-02-09
Clifford Wolf
Updated command reference in manual
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2015-02-09
Clifford Wolf
Various presentation fixes
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2015-02-08
Clifford Wolf
Fixed iterator invalidation bug in "rename" command
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2015-02-08
Clifford Wolf
CodingReadme update
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2015-02-08
Clifford Wolf
Fixed bug in "show -format .."
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2015-02-08
Clifford Wolf
Added new APIs to changelog
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2015-02-08
Clifford Wolf
Fixed eval_select_op() api
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2015-02-08
Clifford Wolf
Added eval_select_args() and eval_select_op()
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2015-02-08
Clifford Wolf
Minor "make vgtest" changes
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2015-02-08
Clifford Wolf
Various ModIndex improvements
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2015-02-08
Clifford Wolf
Added Yosys 0.5 Changelog
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2015-02-08
Clifford Wolf
Various updates to CodingReadme
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2015-02-08
Clifford Wolf
Added equiv_add
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2015-02-07
Clifford Wolf
Ignore explicit assignments to constants in HDL code
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2015-02-07
Clifford Wolf
Fixed a bug with autowire bit size
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2015-02-07
Clifford Wolf
fixed typo
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2015-02-07
Clifford Wolf
Added "yosys-config --build modname.so cppsources.."
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2015-02-07
Clifford Wolf
Added SigSpec::has_const()
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2015-02-07
Clifford Wolf
Cleanup in add_share_file make macro
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2015-02-07
Clifford Wolf
Removed "make mklibyosys"
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2015-02-07
Clifford Wolf
Improved building of plugins
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2015-02-07
Clifford Wolf
Added "make uninstall"
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2015-02-07
Clifford Wolf
Added cell->known(), cell->input(portname), cell->outpu...
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2015-02-06
Clifford Wolf
Added "select -read"
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2015-02-05
Clifford Wolf
Auto-detect TCL version
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2015-02-04
Clifford Wolf
Added onehot attribute
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2015-02-04
Clifford Wolf
Fixed opt_clean performance bug
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2015-02-04
Clifford Wolf
Disabled (unused) Xilinx tristate buffers
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2015-02-03
Clifford Wolf
Using design->selected_modules() in opt_*
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2015-02-03
Clifford Wolf
Skip blackbox modules in design->selected_modules()
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2015-02-03
Clifford Wolf
Added "yosys -L logfile"
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2015-02-01
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-02-01
Clifford Wolf
no support for 6-series xilinx devices
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2015-02-01
Clifford Wolf
Merge pull request #48 from rubund/master
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2015-02-01
Clifford Wolf
Improved performance in equiv_simple
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2015-02-01
Ruben Undheim
Fixed typos found by lintian
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2015-02-01
Clifford Wolf
Removed old XST-based xilinx examples
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2015-02-01
Clifford Wolf
Added Xilinx example for Basys3 board
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2015-02-01
Clifford Wolf
Added EDIF backend support for multi-bit cell ports
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2015-02-01
Clifford Wolf
Added missing ports and parameters to xilinx brams
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2015-02-01
Clifford Wolf
Added "make mklibyosys", some minor API changes
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2015-01-31
Clifford Wolf
Minor README changes
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2015-01-31
Clifford Wolf
Removed TODO list from README file
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2015-01-31
Clifford Wolf
Added yosys_banner(), Updated Copyright range
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2015-01-31
Clifford Wolf
Added <algorithm> include to hashlib.h
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2015-01-31
Clifford Wolf
Using selections in "ls" command
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2015-01-31
Clifford Wolf
Shorter "dump" options
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2015-01-31
Clifford Wolf
Bugfix in opt_const $eq -> buffer code
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2015-01-31
Clifford Wolf
Log msg change
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2015-01-31
Clifford Wolf
Fixed equiv_make for partially undriven nets (e.g....
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2015-01-31
Clifford Wolf
Added "equiv_induct -undef"
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2015-01-31
Clifford Wolf
Added "equiv_simple -undef"
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2015-01-31
Clifford Wolf
Added "equiv_make -blacklist <file> -encfile <file>"
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2015-01-30
Clifford Wolf
Synced RTLIL::unescape_id() to log_id() behavior
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2015-01-30
Clifford Wolf
Added "fsm -encfile"
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2015-01-30
Clifford Wolf
More log_id() stuff
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2015-01-30
Clifford Wolf
Some cleanups in log.cc
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2015-01-27
Clifford Wolf
Improved an error message
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2015-01-27
Clifford Wolf
Fixed bug in equiv_miter
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2015-01-27
Clifford Wolf
Added "sat -show-ports"
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2015-01-27
Clifford Wolf
Bugfix in resource sharing test
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2015-01-27
Clifford Wolf
Updaed ABC to hg rev 61ad5f908c03
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2015-01-25
Clifford Wolf
Rethrow with "catch(...) throw;"
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2015-01-25
Clifford Wolf
Added equiv_remove
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2015-01-25
Clifford Wolf
Added equiv_miter
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2015-01-24
Clifford Wolf
Added ENABLE_NDEBUG makefile options
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2015-01-24
Clifford Wolf
Added #ifdef NDEBUG for log_assert()
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2015-01-24
Clifford Wolf
Fixed xilinx FDSE sim model
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2015-01-23
Clifford Wolf
Various equiv_* improvements
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2015-01-23
Clifford Wolf
Added dict/pool.sort()
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2015-01-22
Clifford Wolf
Improvements in equiv_make, equiv_induct
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2015-01-22
Clifford Wolf
Improved xdot calling
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2015-01-22
Clifford Wolf
Added equiv_induct
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2015-01-22
Clifford Wolf
Various equiv_simple improvements
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2015-01-22
Clifford Wolf
Moved equiv stuff to passes/equiv/
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2015-01-21
Clifford Wolf
Progress in equiv_simple
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2015-01-21
Clifford Wolf
Fixed opt_muxtree performance bug
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2015-01-20
Clifford Wolf
Faster "make clean-abc"
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2015-01-20
Clifford Wolf
README stuff
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2015-01-19
Clifford Wolf
Added equiv_simple
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2015-01-19
Clifford Wolf
Added equiv_status
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2015-01-19
Clifford Wolf
Added equiv_make command
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2015-01-19
Clifford Wolf
Added $equiv cell type
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2015-01-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-01-18
Clifford Wolf
Various cleanups in xilinx techlib
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2015-01-18
Clifford Wolf
Refactoring of memory_bram and xilinx brams
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2015-01-18
Clifford Wolf
Merge pull request #47 from mschmoelzer/master
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2015-01-18
Martin Schmölzer
Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
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2015-01-18
Clifford Wolf
improvements in muxtree/select_leaves test
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2015-01-18
Clifford Wolf
Improvements in opt_muxtree
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2015-01-18
Clifford Wolf
More opt_muxtree cleanups
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2015-01-18
Clifford Wolf
Added hashlib::idict<>
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2015-01-18
Clifford Wolf
Various cleanups and improvements in opt_muxtree
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2015-01-17
Clifford Wolf
Added synth_xilinx -retime -flatten
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