2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - generate PCI node |
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2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - Generate energy controller... |
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2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - autogenerate RealView Platform... |
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2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - Generate memory node |
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2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - Generate cpus node |
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2018-01-29 |
Glenn Bergmans | arm: DT autogeneration - Device Tree generation methods |
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2018-01-29 |
Glenn Bergmans | ext: DT autogeneration - Add PyFtd to m5 space |
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2018-01-29 |
Curtis Dunham | arm: make Arm GenericTimer a ClockedObject |
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2018-01-27 |
Gabe Black | base: Add an "override" to name() in the HardBreakpoint... |
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2018-01-27 |
Gabe Black | base: Get bitunions to compile on clang 3.8. |
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2018-01-25 |
Hanhwi Jang | util: Implement Lua module for m5ops. |
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2018-01-23 |
Swapnil Haria | arch-x86: Adding clflush, clflushopt, clwb instructions |
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2018-01-23 |
Gabe Black | arch: Remove the "arch/tlb.hh" switching header. |
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2018-01-23 |
Gabe Black | tarch, mem: Abstract the data stored in the SE page... |
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2018-01-23 |
Gabe Black | x86, mem: Rewrite the multilevel page table class. |
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2018-01-20 |
Hanhwi Jang | util: Implement PIC version of m5ops for X86. |
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2018-01-20 |
Gabe Black | x86, mem: Don't try to force physical addresses on... |
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2018-01-20 |
Gabe Black | x86, mem: Get rid of PageTableOps::getBasePtr. |
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2018-01-20 |
Gabe Black | x86, mem: Pass the multi level page table layout in... |
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2018-01-20 |
Gabe Black | arch, mem: Make the page table lookup function return... |
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2018-01-20 |
Gabe Black | base: Hide the BitUnion::__StorageType type. |
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2018-01-20 |
Gabe Black | arm, base: Generalize and move the BitUnion hash struct. |
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2018-01-20 |
Gabe Black | sim: Use the new BitUnion templates in serialize.hh. |
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2018-01-20 |
Gabe Black | base: Enable specializing templates on BitUnion types. |
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2018-01-20 |
Gabe Black | base: Rework bitunions so they can be more flexible. |
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2018-01-20 |
Gabe Black | sim, arch, base: Refactor the base remote GDB class. |
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2018-01-19 |
Gabe Black | arch, mem, sim: Consolidate and rename the SE mode... |
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2018-01-18 |
Andreas Sandberg | util: Add an option to specify paths in list_changes.py |
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2018-01-17 |
Gabe Black | mem: Change the multilevel page table to inherit from... |
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2018-01-16 |
Alec Roelke | arch-riscv: Fix floating-poing op classes |
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2018-01-16 |
Alec Roelke | arch-riscv: Fix floating-point conversion bugs |
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2018-01-16 |
Gabe Black | sim: Simplify registerThreadContext a little bit. |
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2018-01-15 |
Gabe Black | mem: Track TLB entries in the lookup cache as pointers. |
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2018-01-15 |
Gabe Black | arch: Fix a fatal_if in most of the arch's process... |
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2018-01-12 |
Xiaoyu Ma | sim: Allow passing a user-defined L2XBar to addTwoLevel... |
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2018-01-11 |
Earl Ou | util/m5: add Android.mk |
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2018-01-11 |
Alec Roelke | arch-riscv: Don't crash when printing unknown CSRs |
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2018-01-11 |
Nikos Nikoleris | mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token... |
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2018-01-11 |
Nikos Nikoleris | mem-ruby: Remove function that maps responses to a... |
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2018-01-11 |
Nikos Nikoleris | mem-ruby: Add support for multiple DMA engines in MESI_... |
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2018-01-11 |
Gabe Black | cpu: Make the CPU's TLB parameter a BaseTLB. |
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2018-01-11 |
Gabe Black | arm, power: Make the python TLB simobjects inherit... |
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2018-01-11 |
Gabe Black | arch,mem: Remove the default value for page size. |
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2018-01-11 |
Gabe Black | arch,mem: Move page table construction into the arch... |
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2018-01-10 |
Chen Zou | configs: Fill in the cpu.isa field in etrace_replay... |
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2018-01-10 |
BKP | style: change C/C++ source permissions to noexec |
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2018-01-10 |
Alec Roelke | arch-riscv: Make use of ImmOp's polymorphism |
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2018-01-10 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of... |
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2018-01-10 |
Tuan Ta | arch-riscv,sim: Support clone syscall in RISC-V |
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2018-01-09 |
Nikos Nikoleris | mem-cache: Prune unnecessary writebacks in exclusive... |
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2018-01-09 |
Hanhwi Jang | util: Add the missing wakecpu m5op in X86. |
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2018-01-09 |
Hanhwi Jang | util: resolve m5op name mismatching in m5op headers. |
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2018-01-09 |
Gabe Black | cpu: Use the NotAnInst flag to avoid passing an inst... |
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2018-01-09 |
Gabe Black | cpu: Add a NotAnInst flag to the BaseDynInst class. |
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2018-01-09 |
Gabe Black | cpu, power: Get rid of the remnants of the EA computati... |
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2018-01-09 |
Gabe Black | arm: Make translateFunctional override the base impleme... |
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2018-01-08 |
Tony Gutierrez | gpu-compute: call createThreads() on cpu objs in apu_se.py |
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2018-01-05 |
Tuan Ta | arch-riscv: Ignore sched_yield syscall in SE mode |
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2018-01-05 |
Tuan Ta | sim: Fix a bug in prlimit syscall in SE mode |
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2018-01-05 |
Tuan Ta | arch-riscv: Ignore set_robust_list and get_robust_list... |
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2018-01-05 |
Tuan Ta | arch-riscv: Add an implementation of set_tid_address... |
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2018-01-05 |
Alec Roelke | arch-riscv: Correct syscall argument reg count |
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2018-01-04 |
Alec Roelke | arch-riscv: Remove "magic" syscall number constant |
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2018-01-02 |
Gabe Black | config: Handle NULL simobject parameters in read_config.py. |
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2018-01-02 |
Gabe Black | config: Fix parsing AddrRange parameters in read_config.py. |
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2018-01-02 |
Gabe Black | config: Add a --checkpoint-dir argument to read_config.py. |
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2017-12-23 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA... |
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2017-12-23 |
Gabe Black | riscv,x86: Stop using the arch Nop machine instruction... |
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2017-12-22 |
Gabe Black | arch,cpu: "virtualize" the TLB interface. |
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2017-12-22 |
Gabe Black | cpu: Use the generic nop static inst instead of decodin... |
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2017-12-22 |
Gabe Black | cpu: Add a pointer to a generic Nop StaticInst. |
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2017-12-21 |
Giacomo Travaglini | arch-arm: Fixed WFE/WFI trapping behaviour |
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2017-12-21 |
Giacomo Travaglini | arch-arm: Hyp routed undef fault need to change its... |
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2017-12-21 |
Giacomo Travaglini | arch-arm: Fix StaticInst encoding() method |
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2017-12-20 |
Gabe Black | cpu: Fix exit_gen.cc which used misc.hh instead of... |
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2017-12-19 |
Giacomo Travaglini | arch-arm: Instruction size methods in StaticInst class |
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2017-12-19 |
Giacomo Travaglini | arch-arm: Change casting type from reinterpret to static |
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2017-12-19 |
Riken Gohil | cpu-tester: Added ExitGen to TrafficGen |
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2017-12-19 |
Riken Gohil | cpu-tester: Refactoring traffic generators into separat... |
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2017-12-15 |
Swapnil Haria | mem-ruby: Support atomic_noncaching acceses in ruby |
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2017-12-14 |
Alec Roelke | arch-riscv: Define AT_RANDOM properly |
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2017-12-14 |
Alec Roelke | arch-riscv: Increase maximum stack size |
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2017-12-14 |
Jason Lowe... | misc: Updates for gcc7.2 for x86 |
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2017-12-14 |
Jason Lowe... | ext: Upgrade PyBind11 to version 2.2.1 |
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2017-12-14 |
Gabe Black | x86: Use operand size 4 when it would be 2 for cmpxchg8b. |
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2017-12-13 |
Andreas Sandberg | scons, tests: Fix occasional linking error |
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2017-12-13 |
Andreas Sandberg | scons, tests: Add support for GTest XML generation |
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2017-12-13 |
Andreas Sandberg | scons: Make sure GTests have the right environment... |
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2017-12-13 |
Gabe Black | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64... |
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2017-12-13 |
Gabe Black | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp... |
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2017-12-13 |
Gabe Black | x86: Rework how "split" loads/stores are handled. |
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2017-12-13 |
Gabe Black | base: Add endianness conversion functions for std:... |
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2017-12-12 |
Gabe Black | tests: Turn fbtest into a gtest and move it to src... |
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2017-12-12 |
Gabe Black | tests: Move the cprintftest unit test into src/base. |
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2017-12-12 |
Gabe Black | tests: Convert the cprintf unit test into a gtest. |
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2017-12-12 |
Gabe Black | tests: Move the trietest unit test into base. |
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2017-12-12 |
Gabe Black | tests: Plumb dumps of the test trie into the gtest... |
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2017-12-12 |
Gabe Black | tests: Convert the trie unit test into a gtest. |
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2017-12-12 |
Gabe Black | tests: Add an implementation of the Logger interface... |
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2017-12-12 |
Gabe Black | misc: Rework the logging functions. |
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