yosys.git
2019-04-08 Eddie HungMerge branch 'undo_pr895' into xc7srl
2019-04-08 Eddie HungUndo #895 by instead setting an attribute
2019-04-08 Eddie HungCope with undoing #895
2019-04-08 Eddie HungRevert "Remove handling for $pmux, since #895"
2019-04-06 Eddie HungCall shregmap twice -- once for variable, another for...
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungAdd retime test
2019-04-05 Eddie HungFix S0 -> S1
2019-04-05 Eddie HungMove dffinit til after abc
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungMove techamp t:$_DFF_?N? to before abc call
2019-04-05 Eddie HungRetry
2019-04-05 Eddie Hung"&nf -D 0" fails => use "-D 1" instead
2019-04-05 Eddie HungResolve @daveshah1 comment, update synth_xilinx help
2019-04-05 Eddie Hungsynth_xilinx to techmap FFs after abc call, otherwise...
2019-04-05 Eddie Hungabc -dff now implies "-D 0" otherwise retiming doesn...
2019-04-05 Eddie Hungtechmap inside map_cells stage
2019-04-05 Clifford WolfAdd "read_ilang -lib"
2019-04-04 Clifford WolfAdded missing argument checking to "mutate" command
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie HungMissing techmap entry in help
2019-04-04 Eddie HungUse soft-logic, not LUT3 instantiation
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie Hungsynth_xilinx to map_cells before map_luts
2019-04-04 Eddie HungCleanup comments
2019-04-04 Eddie Hungt:$dff* -> t:$dff t:$dffe
2019-04-03 Eddie HungRemove handling for $pmux, since #895
2019-04-03 Eddie Hung-nosrl meant when -nobram
2019-04-03 Eddie HungRemove duplicate STARTUPE2
2019-04-03 Eddie HungDisable shregmap in synth_xilinx if -retime
2019-04-03 Eddie HungAdd changelog entry
2019-04-03 Eddie HungMerge pull request #913 from smunaut/fix_proc_mux
2019-04-03 Sylvain Munautproc_mux: Fix crash when trying to optimize non-existan...
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates
2019-04-02 David Shahmemory_bram: Consider read enable for address expansion...
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog...
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
2019-03-29 Clifford WolfBuild Verilog parser with -DYYMAXDEPTH=100000, fixes...
2019-03-28 Clifford WolfMerge pull request #901 from trcwm/libertyfixes
2019-03-28 Clifford WolfMerge pull request #903 from YosysHQ/bram_reset_transp
2019-03-27 David Shahmemory_bram: Reset make_transp when growing read ports
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Clifford WolfAdd "read -verific" and "read -noverific"
2019-03-27 Clifford WolfAdd "rename -output"
2019-03-27 Clifford WolfImprove "rename" help message
2019-03-26 Clifford WolfAdd "cutpoint -undef"
2019-03-26 Clifford WolfAdd "hdlname" attribute
2019-03-26 Clifford WolfFix "verific -extnets" for more complex situations
2019-03-25 Eddie Hungsynth_xilinx to use shregmap with -minlen 3
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-25 Clifford WolfAdd "cutpoint" pass
2019-03-25 Eddie HungCreate one $shiftx per bit in width
2019-03-25 Clifford WolfMerge pull request #896 from YosysHQ/transp_fixes
2019-03-25 Clifford WolfMerge pull request #897 from trcwm/libertyfixes
2019-03-25 Niels Moseleyspaces -> tabs
2019-03-25 Niels MoseleyEOL is now accepted as ';' replacement on lines that...
2019-03-24 Niels MoseleyUpdated the liberty parser to accept [A:B] ranges ...
2019-03-24 David Shahmemory_bram: Fix multiclock make_transp
2019-03-23 Eddie HungAdd a pmux-to-shiftx optimisation to proc_mux
2019-03-23 Eddie HungCope with SHREG not having E port; Revert $pmux fine...
2019-03-23 Clifford WolfAdd "mutate -none -mode", "mutate -mode none"
2019-03-23 Clifford WolfAdd "mutate -s <filename>"
2019-03-23 Clifford WolfMerge pull request #893 from YosysHQ/clifford/btormeminit
2019-03-23 Clifford WolfAdd support for memory initialization to write_btor
2019-03-23 Clifford WolfFix BTOR output tags syntax in writye_btor
2019-03-23 Clifford WolfAdd RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend...
2019-03-23 Eddie HungAdd support for SHREGMAP+$mux, also fine tune $pmux
2019-03-23 Eddie HungLeftover printf
2019-03-23 Eddie HungFixes for multibit
2019-03-23 Eddie HungWorking for 1 bit
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-22 Clifford WolfTrim init attributes when resizing FFs in "wreduce...
2019-03-21 Eddie HungAdd '-nosrl' option to synth_xilinx
2019-03-21 Clifford WolfFix mem2reg handling of memories with upto data ports...
2019-03-21 Clifford WolfImprove "read_verilog -dump_vlog[12]" handling of upto...
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-03-21 Eddie HungOpt
2019-03-20 Eddie HungFix spacing
2019-03-20 Eddie HungFine tune cells_map.v
2019-03-20 Eddie HungRevert $__SHREG_ to orig; use $__XILINX_SHREG for varia...
2019-03-20 Eddie HungAdd support for variable length Xilinx SRL > 128
2019-03-19 Eddie HungRestore original synth_xilinx commands
2019-03-19 Eddie HungFix spacing
2019-03-19 Eddie Hungshregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-19 Eddie HungFix INIT for variable length SRs that have been bumped...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMake output port a non chain user
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
next