yosys.git
2019-10-05 Eddie HungRestore optimisation for sigM.empty()
2019-10-05 Eddie HungRetry on fixing TODOs
2019-10-05 Eddie HungRevert "Fix TODOs"
2019-10-05 Eddie HungMore comments, cleanup
2019-10-05 Eddie HungFix TODOs
2019-10-05 Eddie HungConsistency
2019-10-05 Eddie HungAdd comments for xilinx_dsp
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-04 Eddie HungFix xilinx_dsp for unsigned extensions
2019-10-04 Eddie HungFix for SigSpec() == SigSpec(State::Sx, 0) to be true...
2019-10-04 Eddie HungAdd Const::{begin,end,empty}()
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-03 Clifford WolfChange smtbmc "Warmup failed" status to "PREUNSAT"
2019-10-03 Clifford WolfUpdate ABC to git rev 623b5e8
2019-10-03 Clifford WolfBump version
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 Clifford WolfAdd "check -allow-tbuf"
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-03 Eddie HungMerge pull request #1423 from YosysHQ/eddie/techmap_rep...
2019-10-03 Eddie Hunglog_dump() to support State enum
2019-10-02 Eddie HungAlso rename cells with _TECHMAP_REPLACE_. prefix, as...
2019-10-02 Eddie HungExtend test with renaming cells with prefix too
2019-10-02 Clifford WolfMerge pull request #1428 from YosysHQ/clifford/fixbtor
2019-10-02 Clifford WolfAdd "check -mapped"
2019-10-02 Clifford WolfFix btor back-end to use "state" instead of "input...
2019-10-01 Miodrag MilanovićMerge pull request #1426 from YosysHQ/mmicko/fix_environ
2019-10-01 Miodrag MilanovicDefine environ, fixes #1424
2019-10-01 David Shahecp5: Fix shuffle_enable port
2019-10-01 David Shahecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 Eddie HungAdd test
2019-10-01 Eddie Hungtechmap wires named _TECHMAP_REPLACE_.<identifier>...
2019-09-30 Eddie HungAdd quick test
2019-09-30 Eddie HungAdd -select option to aigmap
2019-09-30 Eddie HungFix typo
2019-09-30 Eddie HungFix for svinterfaces
2019-09-30 Eddie Hungmodule->derive() to be lazy and not touch ast if alread...
2019-09-30 Eddie HungUpdate doc for equiv_opt
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 whitequarkrpc: new frontend.
2019-09-30 whitequarklibs: import json11.
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfBump version
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Clifford WolfMerge pull request #1417 from YosysHQ/clifford/fixasync...
2019-09-30 Clifford WolfFix $dlatch handling in async2sync
2019-09-30 Eddie HungAdd latch test modified from #1363
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Miodrag MilanovicFix reading aig files on windows
2019-09-29 Miodrag MilanovicOpen aig frontend as binary file
2019-09-29 Miodrag MilanovićMerge pull request #1413 from YosysHQ/mmicko/backend_bi...
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-29 Henner ZellerAvoid work in replace() if rules empty.
2019-09-28 Miodrag MilanovicAdd aiger and protobuf backends binary support
2019-09-28 Miodrag MilanovicSupport binary files for backends, fixes #1407
2019-09-28 Eddie HungFix box name
2019-09-27 Eddie HungRe-order
2019-09-27 Eddie HungMissing (* mul2dsp *) for sliceB
2019-09-27 Eddie Hungequiv_opt to call async2sync when not -multiclock like...
2019-09-27 Eddie HungOoops AREG and BREG to default to -1
2019-09-27 Aman GoelCorrects btor2 backend
2019-09-27 Marcin KościelnickiFix _TECHMAP_REMOVEINIT_ handling.
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-09-27 Miodrag MilanovićMerge pull request #1409 from YosysHQ/mmicko/fix_getopt...
2019-09-27 Miodrag MilanovicChange order of parameters, to work on other os
2019-09-27 Clifford WolfMerge pull request #1404 from YosysHQ/fix_gzip_macos
2019-09-26 Eddie HungUpdate doc with max cascade chain of 20
2019-09-26 Eddie HungDo not always zero out C (e.g. during cascade breaks)
2019-09-26 Eddie HungUpdate doc
2019-09-26 Eddie HungZero out ports
2019-09-26 Eddie Hungxilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 Eddie HungTry recursive pmgen for P cascade
2019-09-26 Eddie HungMissing an '&'
2019-09-26 Eddie HungCombine 'flatten' & 'coarse' labels in synth_ecp5 so...
2019-09-26 Miodrag MilanovicMake read/write gzip files on macos works, fixes #1357
2019-09-26 Eddie HungTypo
2019-09-26 Eddie HungCREG to check for \keep
2019-09-26 Eddie HungRemove newline
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-26 Eddie Hungmul2dsp.v slice names
2019-09-26 Eddie HungDo not die if DSP48E1.P has no users (would otherwise...
2019-09-26 Eddie HungReject if (* init *) present
2019-09-26 Eddie HungRemove unnecessary check for A_SIGNED != B_SIGNED;...
2019-09-26 Eddie HungRevert "Remove _TECHMAP_CELLTYPE_ check since all ...
2019-09-26 Eddie HungRevert "No need for $__mul anymore?"
2019-09-26 Eddie HungRework xilinx_dsp postAdd for new wreduce call
2019-09-26 Eddie HungOnly wreduce on t:$add
2019-09-25 Eddie HungRemove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 Eddie HungFix memory issue since SigSpec& could be invalidated
2019-09-25 Eddie HungMerge pull request #1401 from SergeyDegtyar/SergeyDegty...
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