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gem5.git
2012-09-25
Djordje Kovacevic
MEM: Put memory system document into doxygen
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2012-09-25
Mrinmoy Ghosh
Cache: add a response latency to the caches
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2012-09-25
Sascha Bischoff
Statistics: Add a function to configure periodic stats...
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2012-09-25
Dam Sunwoo
ARM: added support for flattened device tree blobs
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2012-09-25
Ali Saidi
O3: Pack the comm structures a bit better to reduce...
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2012-09-25
Ali Saidi
mem: Add a gasket that allows memory ranges to be re...
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2012-09-25
Ali Saidi
ARM: Squash outstanding walks when instructions are...
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2012-09-25
Sascha Bischoff
Util: Added script to semantically diff two config...
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2012-09-25
Andreas Sandberg
arm: Use a static_assert to test that miscRegName[...
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2012-09-25
Andreas Sandberg
base: Check for static_assert support and provide fallback
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2012-09-25
Andreas Sandberg
sim: Move CPU-specific methods from SimObject to the...
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2012-09-25
Andreas Sandberg
sim: Remove SimObject::setMemoryMode
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2012-09-25
Djordje Kovacevic
CPU: Add abandoned instructions to O3 Pipe Viewer
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2012-09-25
Nathanael Premillieu
ARM: Inst writing to cntrlReg registers not set as...
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2012-09-25
Ali Saidi
ARM: Predict target of more instructions that modify PC.
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2012-09-25
Ali Saidi
gem5: Update the README file to be a bit less out-of...
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2012-09-25
Andreas Sandberg
build: Add missing dependencies when building param...
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2012-09-24
Andreas Hansson
Stats: Update stats for twosys-tsunami after setting...
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2012-09-24
Andreas Hansson
Regression: Set the clock for twosys-tsunami CPUs
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2012-09-23
Joel Hestness
RubyPort and Sequencer: Fix draining
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2012-09-21
Andreas Hansson
SimpleDRAM: A basic SimpleDRAM regression
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2012-09-21
Andreas Hansson
DRAM: Introduce SimpleDRAM to capture a high-level...
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator regression
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator
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2012-09-21
Andreas Hansson
Mem: Tidy up bus member variables types
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2012-09-21
Andreas Hansson
Scons: Verbose messages when dependencies are not installed
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2012-09-21
Lluc Alvarez
SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex
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2012-09-20
Anthony Gutierrez
bus: removed outdated warn regarding 64 B block sizes
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2012-09-19
Andreas Hansson
Mem: Remove the file parameter from AbstractMemory
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2012-09-19
Andreas Hansson
AddrRange: Transition from Range<T> to AddrRange
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2012-09-19
Andreas Hansson
AddrRange: Simplify Range by removing stream input...
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2012-09-19
Andreas Hansson
AddrRange: Remove unused range_multimap
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2012-09-19
Andreas Hansson
AddrRange: Simplify AddrRange params Python hierarchy
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2012-09-19
Nilay Vaish
ruby: eliminate typedef integer_t
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2012-09-19
Nilay Vaish
ruby: avoid using g_system_ptr for event scheduling
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2012-09-18
Andreas Hansson
Stats: Update stats to reflect SimpleMemory bandwidth
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2012-09-18
Andreas Hansson
Mem: Add a maximum bandwidth to SimpleMemory
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2012-09-14
Andreas Hansson
gcc: Enable Link-Time Optimization for gcc >= 4.6
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2012-09-14
Andreas Hansson
scons: Add a target for google-perftools profiling
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2012-09-14
Andreas Hansson
scons: Restructure ccflags and ldflags
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2012-09-14
Andreas Hansson
scons: Use c++0x with gcc >= 4.4 instead of 4.6
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2012-09-13
Andreas Hansson
Stats: Remove the reference stats that are no longer...
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2012-09-13
Joel Hestness
se.py Ruby: Connect TLB walker ports
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2012-09-13
Joel Hestness
Standard Switch: Drain the system before switching...
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2012-09-13
Joel Hestness
Base CPU: Initialize profileEvent to NULL
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2012-09-12
Jason Power
Ruby: Modify Scons so that we can put .sm files in...
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2012-09-12
Anthony Gutierrez
stats: remove duplicate instruction stats from the...
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2012-09-11
Nilay Vaish
se.py: removes error in passing options to a binary
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2012-09-11
Andreas Hansson
clang: Fix issues identified by the clang static analyzer
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2012-09-11
Andreas Hansson
Checkpoint: Pass maxtick to avoid undefined variable
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2012-09-11
Lena Olson
Cache: Split invalidateBlk up to seperate block vs...
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2012-09-11
Nilay Vaish
x86 Regressions: Update stats due to register predication
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2012-09-11
Nilay Vaish
X86: make use of register predication
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2012-09-11
Nilay Vaish
x86: Add a separate register for D flag bit
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2012-06-03
Nilay Vaish
ISA Parser: Allow predication of source and destination...
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2012-09-11
Nilay Vaish
Ruby: Use uint32_t instead of uint32 everywhere
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2012-09-11
Nilay Vaish
Ruby: Use uint8_t instead of uint8 everywhere
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2012-09-10
Nilay Vaish
Regression: Updates due to changes to Ruby memory contr...
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2012-09-10
Nilay Vaish
Ruby System: Convert to Clocked Object
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2012-09-10
Nilay Vaish
Ruby Slicc: remove the call to cin.get() function
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2012-09-10
Andreas Hansson
Ruby: Bump the stats after recent memory controller...
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2012-09-10
Marco Elver
Mem: Allow serializing of more than INT_MAX bytes
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2012-09-10
Palle Lyckegaard
NetBSD: Build on NetBSD
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2012-09-10
Andreas Hansson
AddrRange: Remove the unused range_ops header
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2012-09-10
Andreas Hansson
Inet: Remove the SackRange and its use
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2012-09-10
Andreas Hansson
Device: Update stats for PIO and PCI latency change
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2012-09-10
Andreas Hansson
Device: Bump PIO and PCI latencies to more reasonable...
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2012-09-09
Nilay Vaish
se.py: support specifying multiple programs via command...
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2012-09-07
Andreas Sandberg
sim: Update the SimObject documentation
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2012-09-07
Andreas Sandberg
sim: Remove the unused SimObject::regFormulas method
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2012-09-07
Ali Saidi
O3: Get rid of incorrect assert in RAS.
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2012-09-07
Ali Saidi
dev: Fix bifield definition in timer_cpulocal.hh
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2012-09-07
Ali Saidi
ARM: Fix the compiler and platform identification for...
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2012-09-07
Ali Saidi
ARM: fix m5 op binary to properly convert 64bit operands
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2012-09-07
Matt Evans
ARM: Fix issue with with way MPIDR is read to include...
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2012-09-07
Ali Saidi
Igbe: Newer kernels seem to allow TSO headers and packe...
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2012-09-07
Djordje Kovacevic
CPU: O3-PipeView.py doesn't display the end of timelines.
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2012-09-07
Krishnendra...
sim: add validation to make sure there is memory where...
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2012-09-07
Ali Saidi
loader: initialize all memory in the ObjectFile objects.
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2012-09-07
Ali Saidi
ARM: Fix one of the timers used in the VExpress EMM...
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2012-09-07
Andreas Hansson
Param: Transition to Cycles for relevant parameters
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2012-09-06
Joel Hestness
stats: Update Ruby regressions for memory controller fix
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2012-09-06
Joel Hestness
Ruby Memory Controller: Fix clocking
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2012-08-28
Jason Power
Ruby: Correct DataBlock =operator
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2012-08-28
Andreas Hansson
Clock: Add a Cycles wrapper class and use where applicable
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2012-08-28
Andreas Hansson
Clock: Rework clocks to avoid tick-to-cycle transformations
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2012-08-28
Andreas Hansson
Port: Stricter port bind/unbind semantics
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2012-08-28
Andreas Hansson
Checker: Bump the realview-o3-checker regression
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2012-08-28
Andreas Hansson
Checker: Fix checker CPU ports
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2012-08-28
Andreas Hansson
swig: Disable unused value warning with llvm 3.1 compilers
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2012-08-28
Anthony Gutierrez
sim: fix overflow check in simulate because Tick is...
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2012-08-27
Nilay Vaish
Ruby: remove README.debugging and Decommissioning_note
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2012-08-27
Nilay Vaish
System: Remove redundant call to startupCPU
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2012-08-27
Nilay Vaish
Ruby: Remove RubyEventQueue
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2012-08-27
Nilay Vaish
Ruby Memory Vector: Allow more than 4GB of memory
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2012-08-25
Nilay Vaish
Regression: updates ruby.stats due to change in virtual...
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2012-08-25
Nilay Vaish
MESI Protocol: Correct the virtual network in profile...
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2012-08-25
Nilay Vaish
MESI Coherence Protocol: Add copyright notice
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2012-08-22
Andreas Hansson
DMA: Refactor the DMA device and align timing and atomic
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2012-08-22
Andreas Hansson
Packet: Remove NACKs from packet and its use in endpoints
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