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libreriscv.git
2021-03-26
lkcl
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2021-03-26
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
rwilbur
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2021-03-25
programmerjake
add cc
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2021-03-25
programmerjake
fix typos
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2021-03-25
lkcl
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2021-03-25
addw@fa2f8cb1790dfac...
Note on open source status of LibreSOC work
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2021-03-25
addw@fa2f8cb1790dfac...
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-25
lkcl
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2021-03-24
Luke Kenneth...
add test html comment
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-21
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-20
lkcl
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2021-03-19
Luke Kenneth...
make dz consistent in SVP64
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2021-03-19
Luke Kenneth...
destination zeroing higher priority than source zeroing
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2021-03-19
lkcl
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2021-03-18
R Veera Kumar
Update Name and RFP project
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2021-03-18
addw@fa2f8cb1790dfac...
Collection of information about non openpower machines
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2021-03-18
Alain D D Williams
Add a new section on non openpower machines
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2021-03-18
Luke Kenneth...
update microwatt sv_decode.vhdl prototype with new...
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2021-03-18
lkcl
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2021-03-18
Luke Kenneth...
add cross-reference to bug #619 to make sure consistenc...
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2021-03-18
Luke Kenneth...
argh really do not like adding autogenerated files
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2021-03-18
Luke Kenneth...
add extra (fake) out2 column to RM SVP64 CSV output
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2021-03-18
Luke Kenneth...
exclude setvl from SVP64 ReMap
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2021-03-18
Luke Kenneth...
add option to create microwatt-formatted VHDL
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2021-03-17
lkcl
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2021-03-17
lkcl
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2021-03-17
lkcl
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2021-03-17
lkcl
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2021-03-17
lkcl
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
rwilbur
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-16
lkcl
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2021-03-13
Luke Kenneth...
corrections to setvl from debugging
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2021-03-13
Luke Kenneth...
expand SVi to 8 bits
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2021-03-13
Luke Kenneth...
sigh have to remove spaces from pseudocode
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2021-03-13
Luke Kenneth...
add simplev to isa pseudocode
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2021-03-13
Luke Kenneth...
add Rc=1 version of setvl
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2021-03-13
Luke Kenneth...
replace OPCD with PO (Primary Opcode)
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2021-03-13
Luke Kenneth...
add first version setvl pseudocode
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2021-03-13
R Veera Kumar
Update: Add completed project, remove from working.
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2021-03-12
Jacob Lifshay
add minor_22.csv
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2021-03-12
lkcl
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2021-03-12
addw@fa2f8cb1790dfac...
Briefly say what ispc is
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2021-03-12
lkcl
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2021-03-12
Luke Kenneth...
stw/std/std/stb must be SRC-RA and SRC-RS
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2021-03-11
lkcl
(no commit message)
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2021-03-10
lkcl
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2021-03-10
lkcl
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