yosys.git
2017-09-01 Andrew ZonenbergRefactoring: moved modules still in cells_sim to cells_...
2017-09-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 Clifford WolfMerge branch 'ChipScan-master'
2017-09-01 Clifford WolfUpdate more stuff to use get_src_attribute() and set_sr...
2017-08-31 Jason Lowdermilkupdated to use get_src_attribute() and set_src_attribute().
2017-08-31 Clifford WolfMerge pull request #399 from azonenberg/counter-extraction
2017-08-31 Andrew ZonenbergMerge branch 'counter-extraction' of github.com:azonenb...
2017-08-31 Andrew Zonenbergextract_counter: Added optimizations to remove unused...
2017-08-30 Andrew ZonenbergMerge branch 'master' of https://github.com/cliffordwol...
2017-08-30 Andrew Zonenbergextract_counter: Minor changes requested to comply...
2017-08-30 Jason LowdermilkMerge remote-tracking branch 'upstream/master'
2017-08-30 Jason Lowdermilkfix indent level
2017-08-30 Clifford WolfMerge pull request #397 from azonenberg/gpak-libfixes
2017-08-30 Clifford WolfAdd {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-29 Jason LowdermilkAdd support for source line tracking through synthesis...
2017-08-29 Andrew ZonenbergFinished refactoring counter extraction to be nice...
2017-08-29 Andrew ZonenbergRefactored extract_counter to be generic vs GreenPAK...
2017-08-29 Andrew ZonenbergRefactoring: Renamed greenpak4_counters pass to extract...
2017-08-28 Andrew ZonenbergReformatted GP_COUNTx_ADV resets to avoid Yosys thinkin...
2017-08-28 Clifford WolfMerge branch 'azonenberg-recover-reduce'
2017-08-28 Clifford WolfRename recover_reduce to extract_reduce, fix args handling
2017-08-28 Clifford WolfMerge branch 'recover-reduce' of https://github.com...
2017-08-28 Clifford WolfFurther improve extract_fa pass
2017-08-28 Clifford WolfMerge pull request #392 from azonenberg/greenpak-portfixes
2017-08-27 Andrew ZonenbergFixed bug causing GP_SPI model to not synthesize
2017-08-27 Robert Ourecover_reduce: Update documentation
2017-08-27 Robert Ourecover_reduce: Reindent using tabs
2017-08-27 Robert Ourecover_reduce: Rename recover_reduce_core to recover_r...
2017-08-27 Robert Ourecover_reduce: Add driver script for the $reduce_...
2017-08-27 Robert Ourecover_reduce_core: Finish implementing the core function
2017-08-27 Robert Ourecover_reduce_core: Initial commit
2017-08-25 Clifford WolfDon't track , ... contradictions through x/z-bits
2017-08-25 Clifford WolfAdd removing of redundant pairs of bits in ==, ===...
2017-08-25 Clifford WolfMerge branch 'extract_fa'
2017-08-25 Clifford WolfFurther improve extract_fa (seems to be fully functiona...
2017-08-25 Clifford WolfRename "adders" to "extract_fa"
2017-08-25 Clifford WolfFix bug in write_smt2 (export logic driving hierarchica...
2017-08-23 Clifford WolfTowards more generic "adder" function extractor
2017-08-22 Clifford WolfAdd experimental adders pass
2017-08-22 Clifford WolfAdd hashlib support for hashing of pools
2017-08-22 Clifford WolfAdd consteval support for $_ANDNOT_ and $_ORNOT_
2017-08-21 Clifford WolfRemove some dead code from fsm_map
2017-08-20 Clifford WolfRename "singleton" pass to "uniquify"
2017-08-18 Clifford WolfMore intuitive handling of "cd .." for singleton modules
2017-08-18 Clifford WolfAdd "sim -zinit -rstlen"
2017-08-18 Clifford WolfMerge branch 'sim'
2017-08-18 Clifford WolfAdd "sim" support for memories
2017-08-18 Clifford WolfAdd Const methods is_fully_zero(), is_fully_def(),...
2017-08-18 Clifford WolfAdd support for assert/assume/cover to "sim" command
2017-08-17 Clifford WolfAdd writeback mode to "sim" command
2017-08-17 Clifford WolfImprove "sim" command
2017-08-16 Clifford WolfMerge pull request #386 from azonenberg/gpak-counters
2017-08-16 Clifford WolfAdd "sim" command skeleton
2017-08-15 Andrew ZonenbergFixed more issues with GreenPAK counter sim models
2017-08-15 Andrew ZonenbergUpdated PGEN model to have level triggered reset (match...
2017-08-15 Andrew ZonenbergFixed bug in GP_COUNTx model
2017-08-15 Andrew ZonenbergFixed bug where GP_COUNTx_ADV would wrap even when...
2017-08-15 Clifford WolfMerge branch 'azonenberg-rmports'
2017-08-15 Clifford WolfMostly coding style related fixes in rmports pass
2017-08-15 Clifford WolfMerge branch 'rmports' of https://github.com/azonenberg...
2017-08-14 Clifford WolfMerge pull request #381 from azonenberg/countfix
2017-08-14 Clifford WolfMerge pull request #383 from azonenberg/abcfnames
2017-08-14 Clifford WolfMerge pull request #382 from azonenberg/jsoniofix
2017-08-14 Clifford WolfMerge pull request #384 from azonenberg/crtechlib
2017-08-14 Robert Oucoolrunner2: Add INVERT parameter to some BUFGs
2017-08-14 Robert Oucoolrunner2: Add FFs with clock enable to cells_sim.v
2017-08-14 Robert Ouabc: Allow +/ filenames in the abc command
2017-08-14 Robert Oujson: Parse inout correctly rather than as an output
2017-08-14 Andrew Zonenbergrmports: Now remove ports from cell instances if we...
2017-08-14 Andrew ZonenbergProcessModule is no longer virtual (why was it in the...
2017-08-14 Andrew Zonenbergrmports now works on all modules in the design, not...
2017-08-14 Andrew ZonenbergUpdated Makefile to reflect opt_rmports being renamed...
2017-08-14 Andrew ZonenbergRenamed opt_rmports pass to rmports
2017-08-14 Andrew ZonenbergFixed typo in GP_COUNT8 sim model
2017-08-14 Andrew ZonenbergFixed typo in error message
2017-08-14 Andrew ZonenbergChanged LEVEL resets for GP_COUNTx to be properly synth...
2017-08-14 Andrew ZonenbergChanged LEVEL resets to be edge triggered anyway
2017-08-14 Andrew ZonenbergAdded level-triggered reset support to GP_COUNTx simula...
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT8_ADV
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT14_ADV
2017-08-14 Andrew ZonenbergFixed typo in last commit
2017-08-14 Andrew ZonenbergFinished initial GP_COUNT8/14/8_ADV/14_ADV sim models...
2017-08-14 Andrew ZonenbergFixed typo in COUNT8 model
2017-08-14 Andrew ZonenbergMoved GP_POR out of digital cells b/c it has delays
2017-08-14 Andrew ZonenbergImproved cells_sim_digital model for GP_COUNT8
2017-08-14 Andrew ZonenbergRefactored GreenPAK4 cells_sim into cells_sim_ams and...
2017-08-14 Andrew ZonenbergImproved handling of constant connections in opt_rmports
2017-08-14 Andrew ZonenbergFixed handling of cell ports that aren't wires
2017-08-14 Andrew Zonenbergopt_rmports: Fixed incorrect handling of multi-bit...
2017-08-14 Andrew ZonenbergRemoved commented out debug code
2017-08-14 Andrew ZonenbergAdded opt_rmports pass (remove unconnected ports from...
2017-08-09 Clifford WolfAdd support for set-reset cell variants to opt_rmdff
2017-08-09 Clifford WolfAuto-detect JSON front-end
2017-08-06 Clifford WolfAdd handling of constant reset signals to opt_rmdff
2017-08-04 Clifford WolfAdd "yosys-smtbmc --smtc-init --smtc-top --noinit"
2017-08-04 Clifford WolfAdd "-undefined dynamic_lookup" to OSX "yosys-config...
2017-07-29 Clifford WolfFix typo in "abc" pass help message
2017-07-28 Clifford WolfAdd merging of "past FFs" to verific importer
2017-07-28 Clifford WolfAdd consolidation of init attributes to opt_clean,...
2017-07-28 Clifford WolfAdd minimal support for PSL in VHDL via Verific
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