yosys.git
2015-02-01 Clifford WolfAdded Xilinx example for Basys3 board
2015-02-01 Clifford WolfAdded EDIF backend support for multi-bit cell ports
2015-02-01 Clifford WolfAdded missing ports and parameters to xilinx brams
2015-02-01 Clifford WolfAdded "make mklibyosys", some minor API changes
2015-01-31 Clifford WolfMinor README changes
2015-01-31 Clifford WolfRemoved TODO list from README file
2015-01-31 Clifford WolfAdded yosys_banner(), Updated Copyright range
2015-01-31 Clifford WolfAdded <algorithm> include to hashlib.h
2015-01-31 Clifford WolfUsing selections in "ls" command
2015-01-31 Clifford WolfShorter "dump" options
2015-01-31 Clifford WolfBugfix in opt_const $eq -> buffer code
2015-01-31 Clifford WolfLog msg change
2015-01-31 Clifford WolfFixed equiv_make for partially undriven nets (e.g....
2015-01-31 Clifford WolfAdded "equiv_induct -undef"
2015-01-31 Clifford WolfAdded "equiv_simple -undef"
2015-01-31 Clifford WolfAdded "equiv_make -blacklist <file> -encfile <file>"
2015-01-30 Clifford WolfSynced RTLIL::unescape_id() to log_id() behavior
2015-01-30 Clifford WolfAdded "fsm -encfile"
2015-01-30 Clifford WolfMore log_id() stuff
2015-01-30 Clifford WolfSome cleanups in log.cc
2015-01-27 Clifford WolfImproved an error message
2015-01-27 Clifford WolfFixed bug in equiv_miter
2015-01-27 Clifford WolfAdded "sat -show-ports"
2015-01-27 Clifford WolfBugfix in resource sharing test
2015-01-27 Clifford WolfUpdaed ABC to hg rev 61ad5f908c03
2015-01-25 Clifford WolfRethrow with "catch(...) throw;"
2015-01-25 Clifford WolfAdded equiv_remove
2015-01-25 Clifford WolfAdded equiv_miter
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options
2015-01-24 Clifford WolfAdded #ifdef NDEBUG for log_assert()
2015-01-24 Clifford WolfFixed xilinx FDSE sim model
2015-01-23 Clifford WolfVarious equiv_* improvements
2015-01-23 Clifford WolfAdded dict/pool.sort()
2015-01-22 Clifford WolfImprovements in equiv_make, equiv_induct
2015-01-22 Clifford WolfImproved xdot calling
2015-01-22 Clifford WolfAdded equiv_induct
2015-01-22 Clifford WolfVarious equiv_simple improvements
2015-01-22 Clifford WolfMoved equiv stuff to passes/equiv/
2015-01-21 Clifford WolfProgress in equiv_simple
2015-01-21 Clifford WolfFixed opt_muxtree performance bug
2015-01-20 Clifford WolfFaster "make clean-abc"
2015-01-20 Clifford WolfREADME stuff
2015-01-19 Clifford WolfAdded equiv_simple
2015-01-19 Clifford WolfAdded equiv_status
2015-01-19 Clifford WolfAdded equiv_make command
2015-01-19 Clifford WolfAdded $equiv cell type
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfVarious cleanups in xilinx techlib
2015-01-18 Clifford WolfRefactoring of memory_bram and xilinx brams
2015-01-18 Clifford WolfMerge pull request #47 from mschmoelzer/master
2015-01-18 Martin SchmölzerAdd "echo-yosys-ver" and "echo-git-rev" Makefile targets.
2015-01-18 Clifford Wolfimprovements in muxtree/select_leaves test
2015-01-18 Clifford WolfImprovements in opt_muxtree
2015-01-18 Clifford WolfMore opt_muxtree cleanups
2015-01-18 Clifford WolfAdded hashlib::idict<>
2015-01-18 Clifford WolfVarious cleanups and improvements in opt_muxtree
2015-01-17 Clifford WolfAdded synth_xilinx -retime -flatten
2015-01-17 Clifford WolfAdded support for memories to flatten (techmap)
2015-01-17 Clifford WolfAdded MUXCY and XORCY support to synth_xilinx
2015-01-17 Clifford WolfFixed a bug in opt_muxtree for "mux forests"
2015-01-17 Clifford WolfImproved opt_muxtree
2015-01-17 Clifford WolfOptimizing no-op cell->setPort()
2015-01-16 Clifford WolfBugfix in dff2dffe
2015-01-16 Clifford WolfAdded cells.lib
2015-01-16 Clifford WolfAdded dff2dffe to synth_xilinx
2015-01-16 Clifford WolfAdded more FF types to xilinx/cells.v
2015-01-16 Clifford WolfFixed xilinx bram clock inverted config
2015-01-16 Clifford WolfAdded FF cells to xilinx/cells_sim.v
2015-01-15 Clifford WolfAdded Xilinx MUXF7 and MUXF8 support
2015-01-15 Clifford WolfAdded "abc -lut w1:w2"
2015-01-15 Clifford WolfFixed handling of foo.__TECHMAP_...
2015-01-15 Clifford WolfIgnoring more system task and functions
2015-01-15 Clifford WolfFixed handling of "input foo; reg [0:0] foo;"
2015-01-15 Clifford WolfConsolidate "Blocking assignment to memory.." msgs...
2015-01-13 Clifford WolfVarious cleanups in synth_xilinx command
2015-01-13 Clifford WolfRe-enabled mux->and/or transform (and fixed lm32 in...
2015-01-13 Clifford WolfTiny fix in vcdcd.pl
2015-01-13 Clifford WolfSmall Makefile typo fix
2015-01-09 Clifford WolfOnly enable code coverage counters on linux
2015-01-08 Clifford WolfMerge pull request #46 from utzig/master
2015-01-08 Fabio UtzigEnable use of homebrew's provided bison if available
2015-01-08 Fabio UtzigEnable bison to be customized
2015-01-08 Fabio UtzigAdd homebrew's libffi paths
2015-01-08 Fabio UtzigAdd homebrew's readline paths
2015-01-07 Clifford WolfAdded add_share_file Makefile macro
2015-01-07 Clifford Wolfadded minimalistic xilinx sim models
2015-01-07 Clifford Wolfdisabled problematic mux -> and/or transform
2015-01-07 Clifford WolfMore Xilinx bram cleanups
2015-01-07 Clifford WolfCleanups in xilinx bram descriptions
2015-01-06 Clifford Wolfmemory_bram hotfix for memories with width 1
2015-01-06 Clifford WolfXilinx RAMB36/RAMB18 memory_bram support complete
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-06 Clifford Wolfsmall fix in xilinx/brams.v
2015-01-06 Clifford Wolffixed compiler warning on non-linux archs
2015-01-06 Clifford Wolfremoved old debug code
2015-01-06 Clifford Wolfhashlib iterator fix
2015-01-06 Clifford Wolfbuild fix for mxe
2015-01-06 Clifford WolfTowards Xilinx bram support
2015-01-06 Clifford WolfVarious small improvements to synth_xilinx
2015-01-06 Clifford WolfTowards Xilinx bram support
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