yosys.git
2014-02-06 Clifford Wolfpresentation progress
2014-02-06 Clifford WolfChanged techmap description from "simple" to "generic"
2014-02-06 Clifford WolfAdded miter -make_outcmp
2014-02-06 Clifford WolfAdded sat -set-init-zero support
2014-02-06 Clifford WolfAdded support for backslash continuation in script...
2014-02-06 Clifford WolfAdded counters sat test case
2014-02-05 Clifford WolfAdded sat -verify and -falsify support for non-prove...
2014-02-05 Clifford WolfAdded expose command
2014-02-05 Clifford Wolfpresentation progress
2014-02-05 Clifford WolfSimplified select "Assertation failed" message generation
2014-02-05 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-05 Clifford WolfMerge pull request #22 from hansiglaser/master
2014-02-05 Clifford WolfAdded BTOR backend README file
2014-02-05 Clifford WolfAdded selection support for r: and selection with relat...
2014-02-05 Johann Glaserbe more verbose for select -assert-any and -assert...
2014-02-05 Johann Glaserimproved help for "select"
2014-02-05 Clifford Wolfpresentation progress
2014-02-05 Clifford Wolfpresentation progress
2014-02-05 Clifford WolfAdded read_verilog -setattr
2014-02-05 Clifford WolfAdded setattr and setparam commands
2014-02-05 Clifford WolfUpdated todo items in README file
2014-02-05 Clifford WolfRemoved old unused files from tests/
2014-02-04 Clifford WolfAdded support for dump -append
2014-02-04 Clifford WolfThrow errors if non-existing selection variables are...
2014-02-04 Clifford WolfAdded select -none
2014-02-04 Clifford Wolfpresentation progress
2014-02-04 Clifford WolfFixed detection of init attribute in opt_rmdff
2014-02-04 Clifford WolfAdded support for inline commands to abc -script
2014-02-04 Clifford Wolfpresentation progress
2014-02-04 Clifford WolfAdded hierarchy -purge_lib option
2014-02-04 Clifford WolfAdded test cases for sat command
2014-02-04 Clifford Wolfadded sat -falsify
2014-02-04 Clifford WolfFixed bug in sequential sat proofs and improved handlin...
2014-02-04 Clifford WolfImproved handling of reg init in opt_share and opt_rmdff
2014-02-03 Clifford Wolfpresentation progress
2014-02-03 Clifford Wolfpresentation progress
2014-02-03 Clifford WolfAddred sat option -ignore_unknown_cells
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-02-03 Clifford WolfReplaced isim with xsim in tests/tools/autotest.sh...
2014-02-02 Clifford WolfMore opt_const -mux_bool features
2014-02-02 Clifford Wolfpresentation progress
2014-02-02 Clifford WolfAdded opt_const -mux_bool
2014-02-02 Clifford WolfAdded support for inverter chains to opt_const
2014-02-02 Clifford WolfAdded RTLIL::SigSpec::to_single_sigbit()
2014-02-02 Clifford WolfOnly generate write-enable $and if WE is not constant...
2014-02-02 Clifford WolfAdded constant-clock case to opt_rmdff
2014-02-02 Clifford Wolfpresentation progress
2014-02-02 Clifford WolfAdded show -notitle option
2014-02-02 Clifford WolfAdded delete command
2014-02-02 Clifford WolfAdded suuport for module attribute matching with A...
2014-02-02 Clifford Wolfpresentation progress
2014-02-02 Clifford Wolfpresentation progress
2014-02-02 Clifford WolfAdded support for blanks after -I and -D in read_verilog
2014-02-01 Clifford WolfFixed a bug in miter command
2014-02-01 Clifford WolfAdded sat -show-inputs and -show-outputs
2014-02-01 Clifford WolfAdded show -color support for cells and finished show...
2014-02-01 Clifford WolfFixed comment/eol parsing in ilang frontend
2014-02-01 Clifford WolfAdded constant size expression support of sized constants
2014-02-01 Clifford WolfAdded note about SystemVerilog assert statement to...
2014-02-01 Clifford WolfAdded miter command
2014-01-31 Clifford WolfProgress on presentation
2014-01-31 Clifford WolfMore changes to techlibs/common/simlib.v for LEC
2014-01-30 Clifford Wolfpresentation progress
2014-01-30 Clifford WolfBugfix in name resolution with generate blocks
2014-01-30 Clifford WolfAdded yosys -H for command list
2014-01-29 Clifford Wolfpresentation progress
2014-01-29 Clifford Wolfpresentation progress
2014-01-29 Clifford WolfTiny change in example script in README
2014-01-29 Clifford WolfAdded -h command line option
2014-01-29 Clifford WolfAdded test comments to techlibs/cmos/cmos_cells.lib
2014-01-29 Clifford WolfUpdated ABC to hg rev e6b09e1
2014-01-28 Clifford WolfAdded read_verilog -icells option
2014-01-28 Clifford WolfMajor rewrite of techlibs/common/simlib.v for LEC ...
2014-01-28 Clifford Wolfpresentation progress
2014-01-28 Clifford WolfRenamed manual/FILES_* directories
2014-01-28 Clifford WolfProgress on presentation
2014-01-27 Clifford WolfProgress on presentation
2014-01-27 Clifford WolfAdded first presentation slides
2014-01-26 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-26 Clifford WolfMerge pull request #21 from hansiglaser/master
2014-01-25 Johann Glaserenabled multiple "-map" for the extract pass
2014-01-25 Johann Glaserbeautified write_intersynth
2014-01-25 Ahmed Irfanroot bug corrected
2014-01-25 Clifford WolfAdded support for // comments in liberty parser
2014-01-24 Clifford WolfMerge branch 'btor'
2014-01-24 Ahmed Irfanremoved regex include
2014-01-24 Ahmed Irfanmerged clifford changes + removed regex
2014-01-24 Clifford WolfUse techmap -share_map in btor scripts
2014-01-24 Clifford WolfMoved btor scripts to backends/btor/
2014-01-24 Clifford WolfRestored Makefile
2014-01-24 Clifford WolfRestored IdString::check()
2014-01-24 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-24 Clifford WolfFixed handling of unsized constants in verilog frontend
2014-01-24 Ahmed Irfanminor change in script
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-20 Clifford WolfFixed algorithmic complexity of AST simplification...
2014-01-20 Ahmed Irfanslice bug corrected
2014-01-20 Ahmed Irfanassert feature
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded hilomap command
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