yosys.git
2018-11-07 Clifford WolfMerge pull request #693 from YosysHQ/rlimit
2018-11-07 Clifford WolfLimit stack size to 16 MB on Darwin
2018-11-06 Clifford WolfMerge pull request #694 from trcwm/dffmap_expr_fix
2018-11-06 Niels MoseleyDFFLIBMAP: changed 'missing pin' error into a warning...
2018-11-06 Clifford WolfRun solver in non-incremental mode whem smtio.py is...
2018-11-06 Clifford WolfUpdate ABC rev to 4d56acf
2018-11-06 Clifford WolfFix for improved smtio.py rlimit code
2018-11-06 Clifford WolfImprove stack rlimit code in smtio.py
2018-11-05 Clifford WolfAllow square brackets in liberty identifiers
2018-11-05 Clifford WolfMerge pull request #691 from arjenroodselaar/stacksize
2018-11-05 Arjen RoodselaarUse conservative stack size for SMT2 on MacOS
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property"
2018-11-04 Clifford WolfAdd proper error message for when smtbmc "append" fails
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell
2018-11-03 ZipCPUMake and dependent upon LSB only
2018-11-03 Niels MoseleyLiberty file newline handling is more relaxed. More...
2018-11-03 Niels MoseleyReport an error when a liberty file contains pin refere...
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen...
2018-11-01 Clifford WolfAdd support for signed $shift/$shiftx in smt2 back-end
2018-10-31 Clifford WolfMerge branch 'igloo2'
2018-10-31 Clifford WolfFix sf2 LUT interface
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support
2018-10-30 Clifford WolfMerge pull request #680 from jburgess777/fix-empty...
2018-10-28 Jon BurgessAvoid assert when label is an empty string
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfFix minor typo in error message
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the...
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-22 whentzefix unhandled std::out_of_range when calling yosys...
2018-10-22 David Shahecp5: Remove DSP parameters that don't work
2018-10-21 David Shahecp5: Add DSP blackboxes
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-20 Ruben UndheimFixed memory leak
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve
2018-10-19 David Shahecp5: Sim model fixes
2018-10-19 David Shahecp5: Add latch inference
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-19 David Shahmemory_bram: Reset make_outreg when growing read ports
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master
2018-10-19 Clifford WolfMerge pull request #670 from rubund/feature/basic_svint...
2018-10-18 rafaeltpadding offset info to memories
2018-10-18 rafaeltpadding offset info to memories
2018-10-18 Ruben UndheimBasic test for checking correct synthesis of SystemVeri...
2018-10-18 Clifford WolfUpdate ABC to git rev 14d985a
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfUpdate ABC to git rev c5b48bb
2018-10-17 Clifford WolfMinor code cleanups in liberty front-end
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect...
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram
2018-10-17 Clifford WolfMerge pull request #641 from tklam/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfWe have 2018 now
2018-10-16 Clifford WolfAfter release is before release
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-16 Clifford WolfYosys 0.8 yosys-0.8
2018-10-16 argamaignore protect endprotect
2018-10-16 Clifford WolfUpdate command reference manual
2018-10-16 David Shahecp5: Disable LSR inversion
2018-10-15 Aman GoelMinor update
2018-10-13 Ruben UndheimHandle FIXME for modport members without type directly...
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-13 argamadetect ff/latch before processing other nodes
2018-10-13 tklamstop check_signal_in_fanout from traversing FFs
2018-10-13 tklamstop check_signal_in_fanout from traversing FFs
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-12 Ruben UndheimFix build error with clang
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-12 David ShahBRAM improvements
2018-10-10 David Shahecp5: Adding BRAM maps for all size options
2018-10-10 David Shahecp5: First BRAM type maps successfully
2018-10-10 David Shahecp5: Script for BRAM IO connections
2018-10-09 David Shahecp5: Adding BRAM initialisation and config
2018-10-08 Tim 'mithro... xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
2018-10-07 Clifford WolfImprove Verific importer blackbox handling
2018-10-05 David Shahecp5: Add blackbox for DP16KD
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-05 Clifford WolfAdd "write_edif -attrprop"
2018-10-05 Clifford WolfMerge pull request #654 from mithro/patch-1
2018-10-05 Clifford WolfFix compiler warning in verific.cc
2018-10-05 Tim AnsellFix misspelling in issue_template.md
2018-10-04 Adrian WheeldonFix IdString M in setup_stdcells()
2018-10-04 Clifford WolfAdd inout ports to cells_xtra.v
2018-10-04 Clifford WolfMerge pull request #650 from mithro/patch-1
2018-10-03 Tim Ansellxilinx: Adding missing inout IO port to IOBUF
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594
2018-10-02 Tom VerbeureFix for issue 594.
2018-10-01 Aman GoelUpdate to .smv backend
2018-10-01 Dan GisselquistAdd read_verilog $changed support
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